AD9822
Rev. B | Page 12 of 20
FUNCTIONAL DESCRIPTION
The AD9822 can be operated in four different modes: 3-channel
CDS mode, 3-channel SHA mode, 1-channel CDS mode, and
1-channel SHA mode. Each mode is selected by programming
the configuration register through the serial interface. For more
information on CDS or SHA mode operation, see the Circuit
Operation section.
3-CHANNEL CDS MODE
In 3-channel CDS mode, the AD9822 simultaneously samples
the red, green, and blue input voltages from the CCD outputs.
The sampling points for each CDS are controlled by CDSCLK1
and CDSCLK2 (see Figure 10 and Figure 11). CDSCLK1’s
falling edge samples the reference level of the CCD waveform,
and CDSCLK2’s falling edge samples the data level of the CCD
waveform. Each CDS amplifier outputs the difference between
the CCD’s reference and data levels. The output voltage of each
CDS amplifier is then level-shifted by an offset DAC. The
voltages are scaled by the three PGAs before being multiplexed
through the 14-bit ADC. The ADC sequentially samples the
PGA outputs on the falling edges of ADCCLK.
The offset and gain values for the red, green, and blue channels
are programmed using the serial interface. The order in which
the channels are switched through the multiplexer is selected by
programming the MUX register.
Timing for this mode is shown in Figure 3. It is recommended
that the falling edge of CDSCLK2 occur coincident with or
before the rising edge of ADCCLK. However, this is not
required to satisfy the minimum timing constraints. The rising
edge of CDSCLK2 should not occur before the previous falling
edge of ADCCLK, as shown by t
ADC2
. The output data latency is
three clock cycles.
3-CHANNEL SHA MODE
In 3-channel SHA mode, the AD9822 simultaneously samples
the red, green, and blue input voltages. The sampling point is
controlled by CDSCLK2. CDSCLK2’s falling edge samples the
input waveforms on each channel. The output voltages from the
three SHAs are modified by the offset DACs and then scaled by
the three PGAs. The outputs of the PGAs are then multiplexed
through the 14-bit ADC. The ADC sequentially samples the
PGA outputs on the falling edges of ADCCLK.
The input signal is sampled with respect to the voltage applied
to the OFFSET pin (see Figure 12). With the OFFSET pin
grounded, a 0 V input corresponds to the ADC’s zero-scale
output. The OFFSET pin may also be used as a coarse offset
adjust pin. A voltage applied to this pin is subtracted from the
voltages applied to the red, green, and blue inputs in the first
amplifier stage of the AD9822. The input clamp is disabled in
this mode. For more information, see the Circuit Operation
section.
Timing for this mode is shown in Figure 5. CDSCLK1
should be grounded in this mode. Although not required,
it is recommended that the falling edge of CDSCLK2 occur
coincident with or before the rising edge of ADCCLK. The
rising edge of CDSCLK2 should not occur before the previous
falling edge of ADCCLK, as shown by t
ADC2
. The output data
latency is three ADCCLK cycles.
The offset and gain values for the red, green, and blue channels
are programmed using the serial interface. The order in which
the channels are switched through the multiplexer is selected by
programming the MUX register.
1-CHANNEL CDS MODE
This mode operates in the same way as the 3-channel CDS
mode. The difference is that the multiplexer remains fixed in
this mode; therefore, only the channel specified in the MUX
register is processed.
Timing for this mode is shown in Figure 4.
1-CHANNEL SHA MODE
This mode operates in the same way as the 3-channel SHA
mode, except the multiplexer remains stationary. Only the
channel specified in the MUX register is processed.
The input signal is sampled with respect to the voltage applied
to the OFFSET pin. With the OFFSET pin grounded, a 0 V input
corresponds to the ADC’s zero-scale output. The OFFSET pin
may also be used as a coarse offset adjust pin. A voltage applied
to this pin is subtracted from the voltages applied to the red,
green, and blue inputs in the first amplifier stage of the AD9822.
The input clamp is disabled in this mode. For more information,
see the Circuit Operation section.
Timing for this mode is shown in Figure 6. CDSCLK1 should be
grounded in this mode of operation.
