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SC16C652BIBS,157

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
SC16C652B_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 1 September 2005 10 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the SC16C652B
compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above
described flow control mechanisms, flow control characters are not placed (stacked) in the
user accessible RX data buffer or FIFO. When using a software flow control the Xon/Xoff
characters cannot be used for data transfer.
In the event that the receive buffer is overfilling and flow control needs to be executed, the
SC16C652B automatically sends an Xoff message (when enabled) via the serial TX
output to the remote modem. The SC16C652B sends the Xoff1/Xoff2 characters as soon
as received data passes the programmed trigger level. To clear this condition, the
SC16C652B will transmit the programmed Xon1/Xon2 characters as soon as receive data
drops below the programmed trigger level.
6.6 Special feature software flow control
A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit
character is detected, it will be placed on the user-accessible data stack along with normal
incoming RX data. This condition is selected in conjunction with EFR[3:0]. Note that
software flow control should be turned off when using this special mode by setting
EFR[3:0] to a logic 0.
The SC16C652B compares each incoming receive character with Xoff2 data. If a match
exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate
detection of a special character. Although Table 9 “SC16C652B internal registers” shows
each X-Register with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register bits LCR[1:0] define the
number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length
selected by LCR[1:0] also determine the number of bits that will be used for the special
character comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive
character.
6.7 Hardware/software and time-out interrupts
The interrupts are enabled by IER[3:0]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C652B
will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to
continuing operations. The ISR provides the current singular highest priority interrupt only.
It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition
can exist where a higher priority interrupt may mask the lower priority CTS/RTS
interrupt(s). Only after servicing the higher pending interrupt will the lower priority
CTS/RTS interrupt(s) be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C652B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive
SC16C652B_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 1 September 2005 11 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Time Out will not occur if the receive FIFO is empty. The time-out counter is reset at the
center of each stop bit received or each time the Receive Holding Register (RHR) is read.
The actual time-out value is 4 character time, including data information length, start bit,
parity bit, and the size of stop bit, that is, 1×, 1.5×, or 2× bit times.
6.8 Programmable baud rate generator
The SC16C652B supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s modem
that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s
ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.
The SC16C652B can support a standard data rate of 921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is capable
of operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is
necessary to use full rail swing on the clock input. The SC16C652B can be configured for
internal or external clock operation. For internal clock oscillator operation, an industry
standard microprocessor crystal is connected externally between the XTAL1 and XTAL2
pins. Alternatively, an external clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom rates (see Table 6).
The generator divides the input 16× clock by any divisor from 1 to (2
16
− 1). The
SC16C652B divides the basic external clock by 16. The basic 16× clock provides table
rates to support standard and custom applications using the same system design. The
rate table is configured via the DLL and DLM internal register functions. Customized baud
rates can be achieved by selecting the proper divisor values for the MSB and LSB
sections of baud rate generator.
Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate. The example in Table 6 shows the
selectable baud rate table available when using a 1.8432 MHz external clock input.
Fig 4. Crystal oscillator connection
002aaa870
C2
47 pF
XTAL1 XTAL2
X1
1.8432 MHz
C1
22 pF
C2
33 pF
XTAL1 XTAL2
1.5 kΩ
X1
1.8432 MHz
C1
22 pF
SC16C652B_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 1 September 2005 12 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
6.9 DMA operation
The SC16C652B FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output
pins. Table 7 and Table 8 show this.
6.10 Loop-back mode
The internal loop-back capability allows on-board diagnostics. In the loop-back mode, the
normal modem interface pins are disconnected and reconfigured for loop-back internally
(see Figure 5). MCR[3:0] register bits are used for controlling loop-back diagnostic testing.
In the loop-back mode, the transmitter output (TX) and the receiver input (RX) are
disconnected from their associated interface pins, and instead are connected together
internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control
inputs pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2) and
Table 6: Baud rate generator programming table using a 1.8432 MHz clock
Output
baud rate
(bit/s)
Output
16× clock divisor
(decimal)
Output
16× clock divisor
(HEX)
DLM
program value
(HEX)
DLL
program value
(HEX)
50 2304 900 09 00
75 1536 600 06 00
110 1047 417 04 17
150 768 300 03 00
300 384 180 01 80
600 192 C0 00 C0
1200 96 60 00 60
2400 48 30 00 30
3600 32 20 00 20
4800 24 18 00 18
7200 16 10 00 10
9600 12 0C 00 0C
19.2 k 6 06 00 06
38.4 k 3 03 00 03
57.6 k 2 02 00 02
115.2 k 1 01 00 01
Table 7: Effect of DMA mode on state of RXRDY pin
Non-DMA mode DMA mode
1 = FIFO empty 0-to-1 transition when FIFO empties
0 = at least 1 byte in FIFO 1-to-0 transition when FIFO reaches trigger level, or time-out occurs
Table 8: Effect of DMA mode on state of
TXRDY pin
Non-DMA mode DMA mode
1 = at least 1 byte in FIFO 0-to-1 transition when FIFO becomes full
0 = FIFO empty 1-to-0 transition when FIFO goes below trigger level
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SC16C652BIBS,157

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Buy SC16C652BIBS,157
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 16CB 2.5V-5V 2CH
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