SC16C652BIBS,157 Datasheet SC16C652BIBS,151, SC16C652BIBS,128, SC16C652BIB48,128 | P19-P21

Product data sheet Rev. 04 — 1 September 2005 19 of 43

Philips Semiconductors

SC16C652B

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

(cont.)

Transmit operation in mode ‘1’: When the SC16C652B is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1), the

TXRDY pin will be a logic 1 when the

transmit FIFO is completely full. It will be a logic 0 when the trigger level has

been reached.

Receive operation in mode ‘1’: When the SC16C652B is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,

or a Receive Time-Out has occurred, the

RXRDY pin will go to a logic 0.

Once activated, it will go to a logic 1 after there are no more characters in the

FIFO.

2 FCR[2] XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic (the transmit shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

1 FCR[1] RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

0 FCR[0] FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default condition)

logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’

when other FCR bits are written to, or they will not be programmed.

Table 12: RCVR trigger levels

FCR[7] FCR[6] RX FIFO trigger level (bytes)

008

0116

1024

1128

Table 13: TX FIFO trigger levels

FCR[5] FCR[4] TX FIFO trigger level (bytes)

0016

018

1024

1130

Table 11: FIFO Control Register bits description

…continued

Bit Symbol Description

Product data sheet Rev. 04 — 1 September 2005 20 of 43

Philips Semiconductors

SC16C652B

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.4 Interrupt Status Register (ISR)

The SC16C652B provides six levels of prioritized interrupts to minimize external software

interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status

bits. Performing a read cycle on the ISR will provide the user with the highest pending

interrupt level to be serviced. No other interrupts are acknowledged until the pending

interrupt is serviced. A lower level interrupt may be seen after servicing the higher level

interrupt and re-reading the interrupt status bits. Table 14 “Interrupt source” shows the

data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources

associated with each of these interrupt levels.

Table 14: Interrupt source

Priority

level

ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

1 000110LSR (Receiver Line Status

2 000100RXRDY (Received Data Ready)

2 001100RXRDY (Receive Data time-out)

3 000010TXRDY (Transmitter Holding

4 000000MSR (Modem Status Register)

5 010000RXRDY (Received Xoff signal)/

Special character

6 100000CTS, RTS change of state

Table 15: Interrupt Status Register bits description

Bit Symbol Description

7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being

used in the 16C450 mode. They are set to a logic 1 when the FIFOs are

enabled in the SC16C652B mode.

logic 0 or cleared = default condition

5:4 ISR[5:4] INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.

ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]

indicates that CTS, RTS have been generated. Note that once set to a

logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.

logic 0 or cleared = default condition

3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the source for a pending interrupt at

interrupt priority levels 1, 2, and 3 (see

Table 14).

logic 0 or cleared = default condition

0 ISR[0] INT status.

logic 0 = an interrupt is pending and the ISR contents may be used as a

pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

Product data sheet Rev. 04 — 1 September 2005 21 of 43

Philips Semiconductors

SC16C652B

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by writing the

appropriate bits in this register.

Table 16: Line Control Register bits description

Bit Symbol Description

7 LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhanced

Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

6 LCR[6] Set break. When enabled, the Break control bit causes a break condition to

be transmitted (the TX output is forced to a logic 0 state). This condition

exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition

5:3 LCR[5:3] Programs the parity conditions (see

Table 17).

2 LCR[2] Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with the

programmed word length (see

Table 18).

logic 0 or cleared = default condition

1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see

Table 19).

logic 0 or cleared = default condition

Table 17: LCR[5:3] parity selection

LCR[5] LCR[4] LCR[3] Parity selection

X X 0 no parity

X 0 1 odd parity

0 1 1 even parity

0 0 1 forced parity ‘1’

1 1 1 forced parity ‘0’

Table 18: LCR[2] stop bit length

LCR[2] Word length (bits) Stop bit length (bit times)

0 5, 6, 7, 8 1

15 1

⁄

1 6, 7, 8 2

Table 19: LCR[1:0] word length

LCR[1] LCR[0] Word length (bits)

00 5

01 6

10 7

11 8

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SC16C652BIBS,157

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Manufacturer:

NXP Semiconductors

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UART Interface IC 16CB 2.5V-5V 2CH

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SC16C652BIBS,157

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