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SC16C652BIBS,157

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
SC16C652B_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 1 September 2005 25 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software flow control selection. When the
Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are
concatenated into two sequential numbers.
Table 23: Enhanced Feature Register bits description
Bit Symbol Description
7 EFR[7] Automatic CTS flow control.
logic 0 = automatic CTS flow control is disabled (normal default condition)
logic 1 = enable automatic CTS flow control. Transmission will stop when
CTS goes to a logical 1. Transmission will resume when the CTS pin returns
to a logical 0.
6 EFR[6] Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be
generated when the receive FIFO is filled to the programmed trigger level and
RTS will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when
data is unloaded below the next lower trigger level (programmed trigger level 1).
The state of this register bit changes with the status of the hardware flow
control.
RTS functions normally when hardware flow control is disabled.
logic
0 = automatic RTS flow control is disabled (normal default condition)
logic 1 = enable automatic RTS flow control
5 EFR[5] Special Character Detect.
logic 0 = special character detect disabled (normal default condition)
logic 1 = special character detect enabled. The SC16C652B compares each
incoming receive character with Xoff2 data. If a match exists, the received
data will be transferred to FIFO and ISR[4] will be set to indicate detection of
special character. Bit-0 in the X-registers corresponds with the LSB bit for the
receive character. When this feature is enabled, the normal software flow
control must be disabled (EFR[3:0] must be set to a logic 0).
4 EFR[4] Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and
MCR[7:5] can be modified and latched. After modifying any bits in the enhanced
registers, EFR[4] can be set to a logic 0 to latch the new values. This feature
prevents existing software from altering or overwriting the SC16C652B
enhanced functions.
logic 0 = disable/latch enhanced features. IER[7:4], ISR[5:4], FCR[5:4], and
MCR[7:5] are saved to retain the user settings, then IER[7:4] ISR[5:4],
FCR[5:4], and MCR[7:5] are set to a logic 0 to be compatible with SC16C554
mode. (Normal default condition.)
logic 1 = enables the enhanced functions. When this bit is set to a logic 1, all
enhanced features of the SC16C652B are enabled and user settings stored
during a reset will be restored.
3:0 EFR[3:0] Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.
Combinations of software flow control can be selected by programming these
bits. See
Table 24.
SC16C652B_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 1 September 2005 26 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
[1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
7.11 SC16C652B external reset condition
Table 24: Software flow control functions
[1]
Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls
0 0 X X No transmit flow control
1 0 X X Transmit Xon1/Xoff1
0 1 X X Transmit Xon2/Xoff2
1 1 X X Transmit Xon1 and Xon2/Xoff1 and Xoff2
X X 0 0 No receive flow control
X X 1 0 Receiver compares Xon1/Xoff1
X X 0 1 Receiver compares Xon2/Xoff2
1011Transmit Xon1/Xoff1
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0111Transmit Xon2/Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
1111Transmit Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
Table 25: Reset state for registers
Register Reset state
IER IER[7:0] = 0
FCR FCR[7:0] = 0
ISR ISR[7:1] = 0; ISR[0] = 1
LCR LCR[7:0] = 0
MCR MCR[7:0] = 0
LSR LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR MSR[7:4] = input signals; MSR[3:0] = 0
SPR SFR[7:0] = 1
DLL DLL[7:0] = X
DLM DLM[7:0] = X
Table 26: Reset state for outputs
Output Reset state
TXA, TXB logic 1
OP2A, OP2B logic 1
RTSA, RTSB logic 1
DTRA, DTRB logic 1
INTA, INTB 3-state condition
SC16C652B_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 1 September 2005 27 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
8. Limiting values
9. Static characteristics
[1] Except XTAL2, V
OL
= 1 V typical.
[2] Sleep current might be higher if there is any activity on the UART data bus during Sleep mode.
Table 27: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage - 7 V
V
n
voltage at any pin GND − 0.3 V
CC
+ 0.3 V
T
amb
ambient temperature operating in free air −40 +85 °C
T
stg
storage temperature −65 +150 °C
P
tot(pack)
total power dissipation per package - 500 mW
Table 28: Static characteristics
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
CC
=
±
10 %; unless otherwise specified.
Symbol Parameter Conditions V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5.0 V Unit
Min Max Min Max Min Max
V
IL(CK)
LOW-level clock input voltage −0.3 0.45 −0.3 0.6 −0.5 0.6 V
V
IH(CK)
HIGH-level clock input voltage 1.8 V
CC
2.4 V
CC
3.0 V
CC
V
V
IL
LOW-level input voltage
(except X1 clock)
−0.3 0.65 −0.3 0.8 −0.5 0.8 V
V
IH
HIGH-level input voltage
(except X1 clock)
1.6 - 2.0 - 2.2 - V
V
OL
LOW-level output voltage on all
outputs
[1]
I
OL
=5mA
(databus)
-----0.4V
I
OL
=4mA
(other outputs)
---0.4--V
I
OL
=2mA
(databus)
-0.4----V
I
OL
= 1.6 mA
(other outputs)
-0.4----V
V
OH
HIGH-level output voltage I
OH
= −5mA
(databus)
----2.4-V
I
OH
= −1mA
(other outputs)
--2.0---V
I
OH
= −800 µA
(data bus)
1.85 -----V
I
OH
= −400 µA
(other outputs)
1.85 -----V
I
LIL
LOW-level input leakage current - ±10 - ±10 - ±10 µA
I
CL
clock leakage current - ±30 - ±30 - ±30 µA
I
CC
supply current f = 5 MHz - 3.5 - 4.5 - 4.5 mA
I
CCsleep
sleep current
[2]
-50-50-50µA
C
i
input capacitance - 5 - 5 - 5 pF
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SC16C652BIBS,157

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Buy SC16C652BIBS,157
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 16CB 2.5V-5V 2CH
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