SC16C652B_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 1 September 2005 6 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
IOW15 12 IWrite strobe (active LOW strobe). A logic 0 transition on this pin will transfer the
contents of the data bus (D0 to D7) from the external CPU to an internal register
that is defined by address bits A0 to A2.
OP2A 32 22 O Output 2 (user-defined). This function is associated with individual channels, A
through B. The state at these pin(s) are defined by the user and through MCR
register bit 3. INTA, INTB are set to the active mode and
OP2 to logic 0 when
MCR[3] is set to a logic 1. INTA, INTB are set to the 3-state mode and
OP2 to a
logic 1 when MCR[3] is set to a logic 0 (see
Table 20 “Modem Control Register bits
description”, bit 3). Since these bits control both the INTA, INTB operation and
OP2 outputs, only one function should be used at one time, INT or OP2.
OP2B 9 7
RESET 36 24 I Reset (active HIGH). A logic 1 on this pin will reset the internal registers and all
the outputs. The UART transmitter output and the receiver input will be disabled
during reset time. (See
Section 7.11 “SC16C652B external reset condition” for
initialization details.)
RIA 41 - I Ring Indicator (active LOW). These inputs are associated with individual UART
channels, A through B. A logic 0 on this pin indicates the modem has received a
ringing signal from the telephone line. A logic 1 transition on this input pin will
generate an interrupt.
RIB 21 -
RTSA 33 23 O Request to Send (active LOW). These outputs are associated with individual
UART channels, A through B. A logic 0 on the
RTS pin indicates the transmitter
has data ready and waiting to send. Writing a logic 1 in the modem control register
MCR[1] will set this pin to a logic 0, indicating data is available. After a reset this
pin will be set to a logic 1. This pin has no effect on the UART’s transmit or receive
operation.
RTSB 22 15
RXA 5 4 I Receive data A, B. These inputs are associated with individual serial channel data
to the SC16C652B receive input circuits, A through B. The RX signal will be a
logic 1 during reset, idle (no data), or when the transmitter is disabled. During the
local loop-back mode, the RX input pin is disabled and TX data is connected to the
UART RX input, internally.
RXB 4 3
RXRDYA31 - O Receive Ready A, B (active LOW). This function provides the RX FIFO/RHR
status for individual receive channels (A to B).
RXRDYn is primarily intended for
monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0 indicates
there is a receive data to read/upload, that is, receive ready status with one or
more RX characters available in the FIFO/RHR. This pin is a logic 1 when the
FIFO/RHR is empty or when the programmed trigger level has not been reached.
This signal can also be used for single mode transfers (DMA mode 0).
RXRDYB 18 -
TXA 7 5 O Transmit data A, B. These outputs are associated with individual serial transmit
channel data from the SC16C652B. The TX signal will be a logic 1 during reset,
idle (no data), or when the transmitter is disabled. During the local loop-back
mode, the TX output pin is disabled and TX data is internally connected to the
UART RX input.
TXB 8 6
TXRDYA43 - O Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR
status for individual transmit channels (A to B).
TXRDYn is primarily intended for
monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual
channel’s
TXRDYA, TXRDYB buffer ready status is indicated by logic 0, that is, at
lease one location is empty and available in the FIFO or THR. This pin goes to a
logic 1 (DMA mode 1) when there are no more empty locations in the FIFO or
THR. This signal can also be used for single mode transfers (DMA mode 0).
TXRDYB 6 -
Table 2: Pin description
…continued
Symbol Pin Type Description
LQFP48 HVQFN32
