LTC4121/LTC4121-4.2
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protection has been engaged) a DC current, I
LOWBAT
, is
applied to the BAT pin from the INTV
CC
supply. When
the battery voltage rises above V
LOWBAT
, the switching
regulator is enabled and charges the battery at a trickle
charge level of 10% of the full scale charge current (in
addition to the DC I
LOWBAT
current). Trickle charging of
the battery continues until the sensed battery voltage rises
above the trickle charge threshold, V
TRKL
, or V
TRKL_42
.
When the battery rises above the trickle charge threshold
the full scale charge current is applied and the DC trickle
charge current is turned off. If the battery remains below
the trickle charge threshold for more than 30 minutes,
charging terminates and the fault status pin is asserted
to indicate a bad battery. After a bad battery fault, the
LTC4121 automatically restarts a new charge cycle once
the failed battery is removed and replaced with another
battery. The LTC4121-4.2 monitors the BATSNS pin volt-
age to sense LOWBAT and TRKL conditions.
Precision Run/Shutdown Control
The LTC4121 remains in a low power disabled mode until
the RUN pin is driven above V
EN
(typically 2.45V). While
the LTC4121 is in disabled mode, current drain from the
battery is reduced to extend battery lifetime, the status pins
are both de-asserted, and the FBG pin is high impedance.
Charging can be stopped at any time by pulling the RUN
pin below 2.25V. The LTC4121 also offers an extremely
low operating current shutdown mode when the RUN pin
is pulled below V
SD
(typically about 0.7V). In this condition
less than 20µA is pulled from the supply at IN. Tie the RUN
pin to a resistive divider from the IN supply to program
the voltage where the LTC4121
turns on. Examples are
shown in Figures 9 and 10.
Differential Under Voltage Lockout
The LTC4121 monitors the difference between the battery
voltage, V
BAT
, and the input supply voltage, V
IN
. If the
difference (V
IN
V
BAT
) falls to ∆V
DUVLO
, all functions are
disabled and the part is forced into shutdown mode until
(V
IN
V
BAT
) rises above the ∆V
DUVLO
rising threshold. The
LTC4121-4.2 monitors the V
BATSNS
and V
IN
pin voltages
to sense DUVLO condition.
OPERATION
User Selectable Switching Regulator Operating
Frequency
The LTC4121 uses a constant-frequency synchronous
step-down switching regulator architecture to pro-
duce high operating efficiency. The nominal operating
frequency, f
OSC
, is programmed by pulling the FREQ pin to
either INTV
CC
or to GND to obtain a switching frequency
of 1.5MHz or 750kHz, respectively. The high operating
frequency allows the use of smaller external components.
Selection of the operating frequency is a trade-off between
efficiency, component size, and margin from the minimum
on-time of the switcher. Operation at lower frequency
improves efficiency by reducing internal gate charge and
switching losses, but requires larger inductance values to
maintain low output ripple. Operation at higher frequency
allows the use of smaller components, but may require
sufficient margin from the minimum on-time at the lowest
duty cycle if fixed-frequency switching is required.
PWM Dropout Detector
If the input voltage approaches the battery voltage, the
LTC4121 may require duty cycles approaching 100%. This
mode of operation is known as dropout. In dropout, the
operating frequency may fall well below the programmed
f
OSC
value. If the top switch remains on for eight clock
cycles, the dropout detector activates and forces the
bottom switch on for the remainder of that clock cycle
or until the inductor current decays to zero. This avoids
a potential source of audible noise when using ceramic
input or output capacitors and prevents the boost sup-
ply capacitor for the top gate drive from discharging. In
dropout operation, the actual charge current may not be
able to reach the full-scale programmed value. In such a
scenario the analog charge current monitor function does
not represent actual charge current being delivered.
Burst Mode
®
Operation
At low charge currents, for example during constant-
voltage mode, the LTC4121 automatically enters Burst
Mode operation. In Burst Mode operation the switcher is
periodically forced into standby mode in order to improve
LTC4121/LTC4121-4.2
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OPERATION
efficiency. The LTC4121 automatically enters Burst Mode
operation after it exits constant-current (CC) mode and as
the charge current drops below about 80mA. Burst Mode
operation is triggered at lower currents for larger PROG
resistors, and depends on the input supply voltage, the
battery voltage, and the selected inductor. Refer to the Burst
Mode Trigger Current and Typical Burst Mode Waveforms
graphs in the Typical Performance Characteristics section
for more information on Burst Mode operation. Burst Mode
operation has some hysteresis and remains engaged for
battery current up to about 150mA, depending on L
SW
,V
IN
and V
BAT
. When operating in Burst Mode, the PROG pin
voltage to average charge current relationship is not well
defined. This may cause the CHRG pin to de-assert early
depending on the amplitude of the burst ripple.
Boost Supply Refresh
The BOOST supply for the top gate drive in the LTC4121
switching regulator is generated by bootstrapping the
BOOST flying capacitor to INTV
CC
whenever the bottom
switch is turned on. This technique provides a voltage of
INTV
CC
from the BOOST pin to the SW pin. In the event
that the bottom switch remains off for a prolonged period
of time, e.g. during Burst Mode operation, the BOOST
supply may require a refresh. Similar to the PWM dropout
timer, the LTC4121 counts the number of clock cycles
since the last BOOST refresh. When this count reaches
32 the next PWM cycle begins by turning on the bottom
side switch first. This pulse refreshes the BOOST flying
capacitor to INTV
CC
and ensures that the top-side gate
driver has sufficient voltage to turn on the top side switch
at the beginning of the next cycle.
Operation without an Input Supply or Shaded Panel
When a battery is the only available power source, care
should be taken to eliminate loading of the IN pin. Load
current on IN drains the battery voltage through the body
diode of the top side power switch as V
IN
falls below V
SW
.
A diode inserted in series with the solar panel, as shown
on the front page schematic, eliminates this discharge
path. Alternatively, a diode may be placed in series with
the BAT pin (
as shown in Figure 8).
LTC4121/LTC4121-4.2
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APPLICATIONS INFORMATION
MPPT Programming
The maximum power-point tracking loop is programmed
by selecting a resistive divider from IN to MPPT to GND
as shown in Figure 4. This user programmable voltage
divider (K
R
) serves to define a fraction of the input voltage
that appears at the MPPT pin:
K
R
=
R
MPPT2
R
MPPT1
+R
MPPT2
=
V
MPPT
V
IN
This fraction of V
IN
is continuously compared against
a fixed fraction of the open-circuit input voltage that is
stored within the LTC4121. A fixed internal resistive divider
(0.1V
IN
) is periodically sampled to compare the open-
circuit input voltage against the user defined fraction of
the loaded input voltage (K
R
V
IN
). On an interval of T
MP
,
the LTC4121 turns off all charger functions reverting to
STANDBY mode. The LTC4121 then waits for a delay, of
about 36ms, PW
MP
, after turning off the charge current to
allow the input supply to recover to its open-circuit volt-
age. Finally, the LTC4121 samples the open-circuit input
voltage V
OC
through a fixed internal divider; K
F
= 1/10.
After sampling the open-circuit voltage, the LTC4121 turns
on all functions and reverts to normal operation. During
normal operation, the stored 0.1V
OC
voltage is compared
against the instantaneous MPPT pin voltage: K
R
V
IN
. If
the MPPT voltage falls below the stored level, the charge
current is reduced to maintain the input voltage. The ratio
of 0.1/K
R
defines the percentage below the open-circuit
voltage where charge current is reduced to maintain the
maximum input power.
Because MPPT operation involves large changes of input
voltage, it is important to ensure that the programmed
maximum power voltage does not violate minimum input
operating conditions: 4.4V or 160mV above the battery
voltage,
whichever is higher.
For example, to select an MPPT set point, V
MP
, at 75%
of the open-circuit voltage, V
OC
, select ratio K
R
using the
following relation:
K
R
=
K
F
75%
=
0.1
0.75
= 0.1333
Using the schematic of Figure 4, this ratio is obtained by
selecting:
R
MPPT1
=
1
K
F
75%
K
F
75%
R
MPPT2
R
MPPT1
= 6.5 • R
MPPT2
Using standard 1% resistors, this is obtained with:
R
MPPT1
= 787k and R
MPPT2
= 121k.
MPPT Error Terms
Uncertainty in programming the MPPT set point is bound
by three error terms: MPPT pin leakage, DAC quantization
error, and the finite offset error in the MPPT error amp. All
error terms are lumped into V
MP(OS)
, with a typical value
of –45mV. This offset at the input to the MPPT error amp
is multiplied by 1/K
R
when observed at the IN regulation
point, V
MP
.
For example, with the same K
R
= 0.1333 (R
MPPT1
= 787k
and R
MPPT2
= 121k) the –45mV V
MP(OS)
error gets am-
plified to –45mV/0.1333 = –338mV at V
IN
from the V
MP
set point of 75% of V
OC
. If V
OC
is 30V, the minimum V
MP
regulation point is about 22.16V, or 73.9% of the open-
circuit voltage.
For solar panel sources, the available power drops off
quickly on the high side, and relatively slowly on the low
side, this is illustrated in the curve in Figure 7. For these
types of sources
, it is usually better to err on the low side
when programming the V
MP
voltage. This is what the
LTC4121 does normally, so most users can simply design
for a V
MP
voltage at (or just below) the level specified by
the solar panel manufacturer. For more information on
solar panels, refer to the panel’s data sheet.

LTC4121EUD#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management 40V 400mA Sync Buck Bat Chr
Lifecycle:
New from this manufacturer.
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