LTC4121/LTC4121-4.2
19
4121fc
For more information www.linear.com/LTC4121
Figure 7. Typical 3W Panel Power vs Voltage
PANEL VOLTAGE (V)
0
POWER (W)
2
3
4
15 25
4121 F07
1
0
5 10
20
75°C
50°C
25°C
APPLICATIONS INFORMATION
The maximum input voltage allowed to maintain constant
frequency operation is:
V
IN(MAX)
=
V
LOWBAT
f
OSC
t
MIN(ON)
where V
LOWBAT
, is the lowest battery voltage where the
switcher is enabled.
Exceeding the minimum on-time constraint does not affect
charge current or battery float voltage, so it may not be
of critical importance in most cases and high switching
frequencies may be used in the design without any fear of
severe consequences. As the sections on Inductor Selection
and Capacitor Selection show, high switching frequencies
allow the use of smaller board components, thus reducing
the footprint of the applications circuit.
Fixed-frequency operation may also be influenced by
dropout and burst mode operation as discussed previously.
Switching Inductor Selection
The primary criterion for switching inductor value selection
in an LTC4121 charger is the ripple current created in that
inductor. Once the inductance value is determined, the
saturation current rating for that inductor must be equal
to or exceed the maximum peak current in the inductor,
I
L(PEAK)
. The peak value of the inductor current is the sum
of the programmed charge current, I
CHG
, plus one half of
the ripple current, ∆I
L
. The peak inductor current must
also remain below the current limit of the LTC4121, I
PEAK
.
I
L(PEAK)
=I
CHG
+
I
L
2
<I
PEAK
The current limit of the LTC4121, I
PEAK
, is at least 585mA
(and at most 1250mA). The typical value of I
PEAK
is illus-
trated in a graph in the Typical Performance Characteristics,
R
SNS
Current Limit vs Temperature.
Input Voltage and Minimum On-Time
The LTC4121 maintains constant frequency operation un-
der most operating conditions. Under certain situations with
high input voltage and high switching frequency selected
and a low battery voltage, the LTC4121 may not be able
to maintain constant frequency operation. These factors,
combined with the minimum on-time of the LTC4121,
impose a minimum limit on the duty cycle to maintain
fixed-frequency operation. The on-time of the top switch
is related to the duty cycle (V
BAT
/V
IN
) and the switching
frequency, f
OSC
in Hz:
t
ON
=
V
BAT
f
OSC
V
IN
When operating from a high input voltage with a low
battery voltage, the PWM control algorithm may attempt
to enforce a duty cycle which requires an on-time lower
than the LTC4121 minimum, t
MIN(ON)
. This minimum
duty cycle is approximately 18% for 1.5MHz operation
or 9% for 750kHz operation. If this occurs, the charge
current and battery voltage remains in regulation, but the
switching duty cycle may not remain fixed, or the switch-
ing frequency may decreases to an integer fraction of its
programmed value.
LTC4121/LTC4121-4.2
20
4121fc
For more information www.linear.com/LTC4121
APPLICATIONS INFORMATION
For a given input and battery voltage, the inductor value
and switching frequency determines the peak-to-peak
ripple current amplitude according to the following formula:
I
L
=
V
IN
V
BAT
( )
V
BAT
f
OSC
V
IN
L
SW
Ripple current is typically set to be within a range of 20%
to 40% of the programmed charge current, I
CHG
. To obtain
a ripple current in this range, select an inductor value us-
ing the nearest standard inductance value available that
obeys the following formula:
L
SW
V
IN(MAX)
V
FLOAT
( )
V
FLOAT
f
OSC
V
IN(MAX)
30% I
CHG
( )
Then select an inductor with a saturation current rating
greater than I
L(PEAK)
.
Input Capacitor
The LTC4121 charger is biased directly from the input
supply at the V
IN
pin. This supply provides large switched
currents, so a high-quality, low ESR decoupling capacitor
is recommended to minimize voltage glitches at V
IN
. Bulk
capacitance is a function of the desired input ripple voltage
(∆V
IN
), and follows the relation:
C
IN(BULK)
=
I
CHG
V
BAT
V
IN
V
IN
(µF)
Input ripple voltages (∆V
IN
) above 0.01V are not recom-
mended. 10µF is typically adequate for most charger
applications, with a voltage rating of 40V.
The input capacitor also forms a pole with the source
impedance that supplies power to V
IN
. This R-C network
must settle within the 36ms PW
MP
period for the LTC4121
to accurately sample the open-circuit voltage at V
IN
.
Adequate settling is usually achieved in 3 to 5 R-C time
constants. To allow the LTC4121 to correctly sample the
open-circuit voltage, limit C
IN
to:
C
IN
< PW
MP
/ (5 • R
SOURCE
),
where R
SOURCE
is the impedance of the power source.
For a solar panel this is the impedance of the panel at the
open-circuit voltage. Looking at a panel's I-V curve, the
source impedance is approximated by (V
OC
V
MP
)/I
MP
.
Typically V
MP
is about 80% of V
OC
, so the solar panels
source impedance can be approximated as:
R
SOURCE
≈ V
OC
/ (5 • I
MP
).
Reverse Blocking
When a fully charged battery is suddenly applied to the
BAT pin, a large in-rush current charges the C
IN
capacitor
through the body diode of the LTC4121 topside power
switch. While the amplitude of this current can exceed
several Amps, the LTC4121 will survive provided the bat-
tery voltage is below about 11V. To completely eliminate
this in-rush current, a blocking P-channel MOSFET should
be placed in series with the BAT pin. When the battery is
the only source of power, this PMOS also serves to de-
crease battery drain current due to any load placed at V
IN
,
conducted through the body diode of the topside power
switch on the LTC4121. The PMOS body diode shown in
Figure8 serves as the blocking component since CHRG is
high impedance when the battery voltage is greater than
the input voltage. When CHRG pulls low, i.e. during most
of a normal charge cycle, the PMOS is on to reduce power
dissipation. The PMOS requires a forward current rating
equal to the programmed charge current and a reverse
breakdown voltage equal to the programmed float voltage.
LTC4121/LTC4121-4.2
21
4121fc
For more information www.linear.com/LTC4121
APPLICATIONS INFORMATION
BAT Capacitor and Output Ripple: C
BAT
The LTC4121 charger output requires bypass capacitance
connected from BAT to GND (C
BAT
). A 22µF ceramic ca-
pacitor is required for all applications. In systems where
the battery can be disconnected from the charger output,
additional bypass capacitance may be desired. In this
type of application, excessive ripple and/or low amplitude
oscillations can occur without additional output bulk
capacitance. For optimum stability, the additional bulk
capacitance should also have a small amount of ESR. For
these applications, place a 100µF low ESR non-ceramic
capacitor (chip tantalum or organic semiconductor capaci-
tors such as Sanyo OS-CONs or POSCAPs) from BAT to
GND, in parallel with the 22µF ceramic bypass capacitor,
or use large ceramic capacitors with an additional small
series ESR resistor of less than 1Ω. This additional bypass
capacitance may also be required in systems where the
battery is connected to the charger with long wires. The
voltage rating of all capacitors applied to C
BAT
must meet
or exceed the battery float voltage.
Boost Supply Capacitor
The BOOST pin provides a bootstrapped supply rail that
provides power to the top gate drivers. The operating volt-
age of the BOOST pin is internally generated from INTV
CC
whenever the SW pin pulls low. This provides a floating
voltage of INTV
CC
above SW that is held by a capacitor
tied from BOOST to SW. A low ESR ceramic capacitor
of 10nF to 33nF is sufficient, with a voltage rating of 6V.
INTV
CC
Supply and Capacitor
Power for the top and bottom gate drivers and most other
internal circuitry is derived from the INTV
CC
pin. A low
ESR ceramic capacitor of 2.2µF is required on the INTV
CC
pin. The INTV
CC
supply has a relatively low current limit
(about
20mA) that is dialed back when INTV
CC
is low to
reduce power dissipation. Do not use the INTV
CC
voltage
to supply power for any external circuitry except for the
NTCBIAS network. When the RUN pin is above V
EN
, the
INTV
CC
supply is enabled, and when INTV
CC
rises above
UV
INTVCC
, the charger is enabled.
Figure 8. Reverse Blocking with a P-Channel MOSFET in Series with the BAT Pin
+
+
BAT
22µF
10µF
4.7µF
2.2µF
R
PROG
R
FB1
49.9k
4.99k*
470k
*ADD 4.99k WHEN MAX BAT VOLTAGE APPROACHES 85%
OF VGS LIMIT FOR Si2343.
R
FB2
Li-Ion
FB
FBG
GND
CHRG
RUN
INTV
CC
V
IN
V
IN
LTC4121
SI2343DS
PROG
BAT
22µF
10µF
4.7µF
2.2µF
R
PROG
49.9k
470k
Li-Ion
BATSNS
GND
CHRG
RUN
INTV
CC
V
IN
V
IN
LTC4121-4.2
SI2343DS
PROG
4121 F08

LTC4121EUD#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management 40V 400mA Sync Buck Bat Chr
Lifecycle:
New from this manufacturer.
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