LTC4121/LTC4121-4.2
22
4121fc
For more information www.linear.com/LTC4121
Calculating IC Power Dissipation
The user should ensure that the maximum rated junction
temperature is not exceeded under all operating conditions.
The thermal resistance of the LTC4121 package (θ
JA
) is
54°C/W; provided that the Exposed Pad is in good thermal
contact with the PCB. The actual thermal resistance in the
application will depend on the forced air cooling and other
heat sinking means, especially the amount of copper on
the PCB to which the LTC4121 is attached. The actual
power dissipation while charging is approximated by the
following formula:
P
D
= V
IN
− V
BAT
•I
TRKL
+ V
IN
•I
IN(SWITCHING)
+R
SNS
•I
2
CHG
+R
DSON(TOP)
•
V
BAT
V
IN
•I
2
CHG
+R
DSON(BOT)
• 1−
V
BAT
V
IN
•I
2
CHG
During trickle charge (V
BAT
< V
TRKL
) the power dissipation
may be significant as I
TRKL
is typically 10mA, however
during normal charging the I
TRKL
term is zero. I
TRKL
is
also zero if V
BAT
approaches INTV
CC
, since I
TRKL
is sourced
from the INTV
CC
LDO.
The junction temperature can be estimated using the fol-
lowing formula:
T
J
= T
A
+ P
D
• Θ
JA
.
where T
A
is the ambient operating temperature.
APPLICATIONS INFORMATION
PCB Layout
To prevent magnetic and electrical field radiation and
high frequency resonant problems, proper layout of the
components connected to the LTC4121 is essential. For
maximum efficiency, the switch node rise and fall times
should be minimized. The following PCB design priority
list will help insure proper topology. Layout the PCB using
the guidelines listed below in this specific order:
1
. V
IN
input capacitor should be placed as close as possible
to the IN pin with the shortest copper traces possible.
The ground return of the input capacitor should be
connected to a solid ground plane.
2
. Place the inductor as close as possible to the SW
pin. Minimize the surface area of the SW pin node.
Make the trace width the minimum needed to support
the programmed charge current, and ensure that the
spacing to other copper traces be maximized to reduce
capacitance from the SW node to any other node.
3
. Place the BAT capacitor adjacent to the BAT pin and
ensure that the ground return feeds to the solid ground
plane.
4
. Route analog ground (RUN pin divider grounded resistor,
the MPPT pin divider, and INTV
CC
capacitor ground) to
the solid ground plane.
5
. It is important to minimize parasitic capacitance on
the PROG pin. The trace connecting to this pin should
be as short as possible with extra wide spacing from
adjacent copper traces.
6
. Keep the GND capacitance of the MPPT pin to a mini-
mum, and reduce coupling from the MPPT pin to any
of the switching pins (SW, BOOST, and CHGSNS) by
routing the MPPT trace away from these signals.
Maximize the copper area connected to the exposed pad.
Place via connections directly under the exposed pad to
connect a large copper ground plane to the LTC4121 to
improve heat transfer.
Example PCB layout files of the LTC4121 are available at
the following link:
http://www.linear.com/product/LTC4121#demoboards.
