Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabil-
ity arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
FEATURES
• 100percentbusutilization
• NowaitcyclesbetweenReadandWrite
• Internalself-timedwritecycle
• IndividualByteWriteControl
• SingleRead/Writecontrolpin
• Clockcontrolled,registeredaddress,
data and control
• Interleavedorlinearburstsequencecontrolus-
ing MODE input
• Threechipenablesforsimpledepthexpansion
and address pipelining
• PowerDownmode
• Commondatainputsanddataoutputs
• CKE pin to enable clock and suspend operation
• JEDEC100-pinTQFP,165-ballPBGAand209-
ball(x72)PBGApackages
• Powersupply:
NVF:V
dd 2.5V(±5%),Vddq2.5V(±5%)
NLF:V
dd3.3V(±5%),Vddq3.3V/2.5V(±5%)
• JTAGBoundaryScanforPBGApackages
• Industrialtemperatureavailable
• Lead-freeavailable
DESCRIPTION
The18Meg'NLF/NVF'productfamilyfeaturehigh-speed,
low-powersynchronousstaticRAMsdesignedtoprovide
a burstable, high-performance, 'no wait' state, device
for networking and communications applications. They
are organized as 256K words by 72 bits, 512K words
by36bitsand1Mwordsby18bits,fabricatedwithISSI's
advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
writetoread.Thisdeviceintegratesa2-bitburstcounter,
high-speedSRAMcore,andhigh-drivecapabilityoutputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKEisHIGH.Inthisstatetheinternal
device will hold their previous values.
AllRead,WriteandDeselectcyclesareinitiatedbytheADV
input.WhentheADVisHIGHtheinternalburstcounter
isincremented.Newexternaladdressescanbeloaded
whenADVisLOW.
Writecyclesareinternallyself-timedandareinitiatedby
the rising edge of the clock inputs and when WEisLOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence.WhentiedHIGH,theinterleavedburstsequence
isselected.WhentiedLOW,thelinearburstsequenceis
selected.
256K x 72, 512K x 36 and 1M x 18
18Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM
NOVEMBER 2013
FAST ACCESS TIME
Symbol Parameter 6.5 7.5 Units
tkq ClockAccessTime 6.5 7.5 ns
tkc CycleTime 7.5 8.5 ns
Frequency 133 117 MHz
