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IS61NVF51236-7.5B3-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 25
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
INSTRUCTION CODES
Code Instruction Description
000 EXTEST CapturestheInput/Outputringcontents.Placestheboundaryscanregisterbe-
tweentheTDIandTDO.ForcesallSRAMoutputstoHigh-Zstate.This
instructionisnot1149.1compliant.
001 IDCODE LoadstheIDregisterwiththevendorIDcodeandplacestheregisterbetweenTDI
andTDO.ThisoperationdoesnotaffectSRAMoperation.
010 SAMPLE-Z CapturestheInput/Outputcontents.Placestheboundaryscanregisterbetween
TDIandTDO.ForcesallSRAMoutputdriverstoaHigh-Zstate.
011 RESERVED DoNotUse:Thisinstructionisreservedforfutureuse.
100
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between
TDIandTDO.DoesnotaffecttheSRAMoperation.Thisinstructiondoesnot
implement1149.1preloadfunctionandisthereforenot1149.1compliant.
101 RESERVED DoNotUse:Thisinstructionisreservedforfutureuse.
110 RESERVED DoNotUse:Thisinstructionisreservedforfutureuse.
111 BYPASS PlacesthebypassregisterbetweenTDIandTDO.Thisoperationdoesnot
affectSRAMoperation.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test/Idle
11 1
11
11
1
1
11
11
1
0
0
0
0
1
00
0
0
0
0
0
0
0
0
0
10
TAP CONTROLLER STATE DIAGRAM
26 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
TAP Electrical Characteristics OvertheOperatingRange
(1,2)
Symbol Parameter Test Conditions Min. Max. Units
Voh1 OutputHIGHVoltage Ioh=–2.0mA 1.7 — V
Voh2 OutputHIGHVoltage Ioh=–100µA 2.1 — V
Vol1 OutputLOWVoltage Iol = 2.0 mA — 0.7V
Vol2 OutputLOWVoltage Iol = 100 µA — 0.2V
VIh InputHIGHVoltage 1.7 Vdd +0.3V
VIl InputLOWVoltage –0.3 0.7V
Ix InputLeakageCurrent VSS ≤VI≤Vddq –10 10 µA
Notes:
1. AllVoltagereferencedtoGround.
2. Overshoot:V
Ih (AC) ≤Vdd+1.5Vfort≤ tTcyc/2,
Undershoot:V
Il (AC) ≤ 0.5Vfort≤ tTcyc/2,
Power-up:V
Ih<2.6VandVdd<2.4VandVddq<1.4Vfort<200ms.
TAP AC ELECTRICAL CHARACTERISTICS
(1,2)
(OVER OPERATING RANGE)
Symbol Parameter Min. Max. Unit
tTcyc TCKClockcycletime 100 — ns
fTf TCKClockfrequency — 10 MHz
tTh TCKClockHIGH 40— ns
tTl TCKClockLOW 40 — ns
tTmSS TMSsetuptoTCKClockRise 10 — ns
tTdIS TDIsetuptoTCKClockRise 10 — ns
tcS CapturesetuptoTCKRise 10 — ns
tTmSh
TMSholdafterTCKClockRise
10 — ns
tTdIh TDIHoldafterClockRise 10 — ns
tch CaptureholdafterClockRise 10 — ns
tTdoV TCKLOWtoTDOvalid — 20 ns
tTdox TCKLOWtoTDOinvalid 0 — ns
Notes:
1. tcS and tch refer to the set-up and hold time requirements of latching data from the boundary scan register.
2.TestconditionsarespeciedusingtheloadinTAPACtestconditions.t
r/tf = 1 ns.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 27
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
DON'T CARE
UNDEFINED
TCK
TMS
TDI
TDO
tTHTL
tTLTH
tTHTH
tMVTH tTHMX
tDVTH tTHDX
1 2 3 4 5 6
t
TLOX
tTLOV
TAP TIMING
20 pF
TDO
GND
50Ω
Vtrig
Z0 = 50Ω
TAP Output Load Equivalent
TAP AC TEST CONDITIONS (2.5V/3.3V)
Inputpulselevels 0to2.5V/0to3.0V
Input rise and fall times 1ns
Inputtimingreferencelevels 1.25V/1.5V
Outputreferencelevels 1.25V/1.5V
Testloadterminationsupplyvoltage 1.25V/1.5V
Vtrig 1.25V/1.5V
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

IS61NVF51236-7.5B3-TR

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Description:
IC SRAM 18M PARALLEL 165TFBGA
Lifecycle:
New from this manufacturer.
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