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IS61NVF51236-7.5B3-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
PIN DESCRIPTIONS
A0, A1 Synchronous AddressInputs.These
pinsmusttiedtothetwoLSBsofthe
address bus.
A Synchronous Address Inputs
CLK SynchronousClock
ADV SynchronousBurstAddressAdvance
BWa-BWd SynchronousByteWriteEnable
WE WriteEnable
CKE Clock Enable
Vss GroundforCore
NC NotConnected
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd SynchronousDataInput/Output
DQPa-DQPd ParityDataI/O
MODE BurstSequenceSelection
Vdd +3.3V/2.5VPowerSupply
VSS GroundforoutputBuffer
Vddq
IsolatedOutputBufferSupply:+3.3V/2.5V
ZZ Snooze Enable
1M x 18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
V
DDQ
Vss
NC
DQPa
DQa
DQa
Vss
V
DDQ
DQa
DQa
Vss
NC
V
DD
ZZ
DQa
DQa
V
DDQ
Vss
DQa
DQa
NC
NC
Vss
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
Vss
NC
NC
DQb
DQb
Vss
V
DDQ
DQb
DQb
NC
V
DD
NC
Vss
DQb
DQb
V
DDQ
Vss
DQb
DQb
DQPb
NC
Vss
V
DDQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BW
b
BWa
CE2
V
DD
Vss
CLK
WE
CKE
OE
ADV
A
A
A
A
MODE
A
A
A
A
A1
A0
NC
NC
Vss
V
DD
NC
NC
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb
DQb
V
DDQ
Vss
DQb
DQb
DQb
DQb
Vss
V
DDQ
DQb
DQb
Vss
NC
V
DD
ZZ
DQa
DQa
V
DDQ
Vss
DQa
DQa
DQa
DQa
Vss
V
DDQ
DQa
DQa
DQPa
DQPc
DQc
DQc
V
DDQ
Vss
DQc
DQc
DQc
DQc
Vss
V
DDQ
DQc
DQc
NC
V
DD
NC
Vss
DQd
DQd
V
DDQ
Vss
DQd
DQd
DQd
DQd
Vss
V
DDQ
DQd
DQd
DQPd
A
A
CE
CE2
BW
d
BWc
BW
b
BW
a
CE2
V
DD
Vss
CLK
WE
CKE
OE
ADV
A
A
A
A
MODE
A
A
A
A
A1
A0
NC
NC
Vss
V
DD
NC
NC
A
A
A
A
A
A
A
512K x 36
PIN CONFIGURATION
100-Pin TQFP
8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
SYNCHRONOUS TRUTH TABLE
(1)
Address
Operation Used CE CE2 CE2 ADV WE BWx OE CKE CLK
NotSelected N/A H X X L X X X L ↑
NotSelected N/A X L X L X X X L ↑
NotSelected N/A X X H L X X X L ↑
NotSelectedContinue N/A X X X H X X X L ↑
BeginBurstRead ExternalAddress L H L L H X L L ↑
ContinueBurstRead NextAddress X X X H X X L L ↑
NOP/DummyRead ExternalAddress L H L L H X H L ↑
DummyRead NextAddress X X X H X X H L ↑
BeginBurstWrite ExternalAddress L H L L L L X L ↑
ContinueBurstWrite NextAddress X X X H X L X L ↑
NOP/WriteAbort N/A L H L L L H X L ↑
WriteAbort NextAddress X X X H X H X L ↑
IgnoreClock CurrentAddress X X X X X X X H ↑
Notes:
1. "X"meansdon'tcare.
2. Therisingedgeofclockissymbolizedby↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE=LmeansWriteoperationinWriteTruthTable.
WE=HmeansReadoperationinWriteTruthTable.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
BURST
READ
DESELECT
BURST
WRITE
BEGIN
READ
BEGIN
WRITE
READ
WRITE
READ
WRITE
BURST
BURST
BURST
DS
DS
DS
READ
DSDS
READ WRITE
WRITE
BURST
BURST
WRITE
READ
STATE DIAGRAM
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47749
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ASYNCHRONOUS TRUTH TABLE
(1)
Operation ZZ OE I/O STATUS
SleepMode H X High-Z
Read L L DQ
L H High-Z
Write L X Din,High-Z
Deselected L X High-Z
Notes:
1. Xmeans"Don'tCare".
2. Forwritecyclesfollowingreadcycles,theoutputbuffersmustbedisabledwithOE, otherwise data
bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. DeselectedmeanspowerSleepModewherestand-bycurrentdependsoncycletime.
WRITE TRUTH TABLE (x18)
Operation WE BWa BWb
READ H X X
WRITEBYTEa L L H
WRITEBYTEb L H L
WRITEALLBYTEs L L L
WRITEABORT/NOP L H H
Notes:
1. Xmeans"Don'tCare".
2. AllinputsinthistablemustbeetsetupandholdtimearoundtherisingedgeofCLK.
WRITE TRUTH TABLE (x36)
Operation WE BWa BWb BWc BWd
READ H X X X X
WRITEBYTEa L L H H H
WRITEBYTEb L H L H H
WRITEBYTEc L H H L H
WRITEBYTEd L H H H L
WRITEALLBYTEs L L L L L
WRITEABORT/NOP L H H H H
Notes:
1. Xmeans"Don'tCare".
2. AllinputsinthistablemustbeetsetupandholdtimearoundtherisingedgeofCLK.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

IS61NVF51236-7.5B3-TR

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IC SRAM 18M PARALLEL 165TFBGA
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