IS61NVF51236-7.5B3-TR Datasheet IS61NLF51236-7.5TQI, IS61NLF102418-6.5TQ, IS61NLF51236-7.5TQLI | P22-P24

22 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. E

10/25/2013

IS61NLF25672/IS61NVF25672

IS61NLF51236/IS61NVF51236

IS61NLF102418/IS61NVF102418

IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)

TheIS61NLFXandIS61NVFXhaveaserialboundary

scanTestAccessPort(TAP)inthePBGApackageonly.

(NotavailableinTQFPpackage.)Thisport operatesin

accordance with

IEEE

Standard1149.1-1900,butdoesnot

includeallfunctionsrequiredforfull1149.1compliance.

Thesefunctionsfromthe

IEEE speciﬁcation

are excluded

because they place added delay in the critical speed path

oftheSRAM.TheTAPcontrolleroperatesinamannerthat

does not conﬂict with the performance of other devices us-

ing1149.1fullycompliantTAPs.TheTAPoperatesusing

JEDECstandard2.5VI/Ologiclevels.

DISABLING THE JTAG FEATURE

TheSRAMcanoperatewithoutusingtheJTAGfeature.

To disable the TAP controller, TCK must be tied LOW

(VSS)topreventclockingofthedevice.TDIandTMSare

internallypulledupandmaybedisconnected.Theymay

alternatelybeconnectedtoVdd through a pull-up resistor.

TDOshouldbeleftdisconnected.Onpower-up,thedevice

will start in a reset state which will not interfere with the

device operation.

31 30 29

. . .

2 1 0

. . . . .

2 1 0

Bypass Register

Instruction Register

Identification Register

Boundary Scan

TAP CONTROLLER

Selection Circuitry Selection Circuitry TDOTDI

TCK

TMS

TAP CONTROLLER BLOCK DIAGRAM

TEST ACCESS PORT (TAP) - TEST CLOCK

ThetestclockisonlyusedwiththeTAPcontroller.Allinputs

arecapturedontherisingedgeofTCKandoutputsare

drivenfromthefallingedgeofTCK.

TEST MODE SELECT (TMS)

TheTMS input is used to send commands to theTAP

controllerandissampledontherisingedgeofTCK.This

pinmaybeleftdisconnectediftheTAPisnotused.The

pinisinternallypulledup,resultinginalogicHIGHlevel.

TEST DATA-IN (TDI)

TheTDI pin is used to serially input information to the

registers and can be connected to the input of any regis-

ter.TheregisterbetweenTDIandTDOischosenbythe

instruction loaded into theTAP instruction register. For

informationon instructionregisterloading,see theTAP

ControllerStateDiagram.TDIisinternallypulledupand

canbedisconnectediftheTAPisunusedinanapplica-

tion.TDIisconnectedtotheMostSignicantBit(MSB)

on any register.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 23

Rev. E

10/25/2013

IS61NLF25672/IS61NVF25672

IS61NLF51236/IS61NVF51236

IS61NLF102418/IS61NVF102418

Boundary Scan Register

Theboundaryscanregisterisconnectedtoallinputand

output pins on the

SRAM

. Several no connect

(NC)

pins are

also included in the scan register to reserve pins for higher

densitydevices.Thex36congurationhasa75-bit-long

contentsoftheRAMInputandOutputringwhentheTAP

controllerisintheCapture-DRstateandthenplacedbe-

tween the

TDI

and

TDO

pins when the controller is moved

to the

Shift-DR

state.TheEXTEST,SAMPLE/PRELOAD

andSAMPLE-Zinstructionscanbeusedtocapturethe

contents of the Input and Output ring.

TheBoundaryScanOrdertablesshowtheorderinwhich

the bits are connected. Each bit corresponds to one of the

bumpsontheSRAMpackage.TheMSBoftheregister

isconnectedtoTDI,andtheLSBisconnectedtoTDO.

Identiﬁcation (ID) Register

The ID register is loaded with a vendor-specic, 32-bit

codeduringtheCapture-DRstatewhentheIDCODEcom-

mandisloadedtotheinstructionregister.TheIDCODE

ishardwiredintotheSRAMandcanbeshiftedoutwhen

theTAPcontrollerisintheShift-DRstate.TheIDregister

has vendor code and other information described in the

IdenticationRegisterDenitionstable.

Scan Register Sizes

Name (x18) (x36) (x72)

Instruction 3 3 3

Bypass 1 1 1

ID 32 32 32

BoundaryScan 75 75

TBD

IDENTIFICATION REGISTER DEFINITIONS

Instruction Field Description 256K x 72 512K x 36 1M x 18

RevisionNumber (31:28) Reservedforversionnumber. xxxx xxxx xxxx

DeviceDepth (27:23) DenesdepthofSRAM.512Kor1M 00110 00111 01000

DeviceWidth (22:18) DenesWidthoftheSRAM.x72,x36orx18 00101 00100 00011

ISSIDeviceID (17:12) Reservedforfutureuse. xxxx xxxxx xxxxx

ISSIJEDECID (11:1) AllowsuniqueidenticationofSRAMvendor. 0011010101 00011010101 00011010101

IDRegisterPresence (0) IndicatethepresenceofanIDregister. 1 1 1

TEST DATA OUT (TDO)

TheTDOoutputpinisusedtoseriallyclockdata-outfrom

theregisters.Theoutputisactivedependingonthecurrent

state of the

TA P

state machine (see

TA P

Controller State

Diagram).TheoutputchangesonthefallingedgeofTCK

andTDOisconnectedtotheLeastSignicantBit(LSB)

of any register.

PERFORMING A TAP RESET

AResetisperformedbyforcingTMSHIGH(Vdd) for ﬁve

risingedgesofTCK.RESETmaybeperformedwhilethe

SRAMisoperatinganddoesnotaffectitsoperation.At

power-up,theTAPisinternallyresettoensurethatTDO

comes up in a high-Z state.

TAP REGISTERS

RegistersareconnectedbetweentheTDIandTDOpins

andallowdatatobescannedintoandoutoftheSRAM

test circuitry. Only one register can be selected at a time

through the instruction registers. Data is serially loaded

intotheTDIpinontherisingedgeofTCKandoutputon

theTDOpinonthefallingedgeofTCK.

Instruction Register

Three-bitinstructionscanbeseriallyloadedintothein-

structionregister.Thisregisterisloadedwhenitisplaced

between the

TDI

and

TDO

pins. (See

TA P

ControllerBlock

Diagram) At power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the

IDCODE instruction if the controller is placed in a reset

state as previously described.

WhentheTAPcontrollerisintheCaptureIRstate,thetwo

least signiﬁcant bits are loaded with a binary “01” pattern

to allow for fault isolation of the board level serial test path.

Bypass Register

Tosavetimewhenseriallyshiftingdatathroughregisters,

itissometimesadvantageoustoskipcertainstates.The

bypass register is a single-bit register that can be placed

betweenTDIandTDOpins.Thisallowsdatatobeshifted

through the

SRAM

withminimaldelay.Thebypassregister

issetLOW(VSS)whentheBYPASSinstructionisexecuted.

24 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. E

10/25/2013

IS61NLF25672/IS61NVF25672

IS61NLF51236/IS61NVF51236

IS61NLF102418/IS61NVF102418

TAP INSTRUCTION SET

Eight instructions are possible with the three-bit instruction

Codetable.Three instructions are listed as

RESERVED

and should not be used and the other ﬁve instructions are

describedbelow.TheTAPcontrollerusedinthisSRAM

isnotfullycompliantwiththe1149.1conventionbecause

some mandatory instructions are not fully implemented.

TheTAPcontrollercannotbeusedtoloadaddress,dataor

control signals and cannot preload the

Input

Output

buf-

fers.The

SRAM

does not implement the

1149.1

commands

EXTEST

INTEST

or the

PRELOAD

portion of

SAMPLE/

PRELOAD

; instead it performs a capture of the

Inputs and

Output

ring when these instructions are executed. Instruc-

tionsareloadedintotheTAPcontrollerduringtheShift-IR

statewhentheinstructionregisterisplacedbetweenTDI

andTDO.Duringthisstate,instructionsareshiftedfrom

theinstructionregisterthroughtheTDIandTDOpins.To

executeaninstructiononceitisshiftedin,theTAPcontrol-

lermustbemovedintotheUpdate-IRstate.

EXTEST

EXTESTisamandatory1149.1instructionwhichistobe

executed whenever the instruction register is loaded with

all0s.BecauseEXTESTisnotimplementedintheTAP

controller,thisdeviceisnot1149.1standardcompliant.

TheTAPcontrollerrecognizesanall-0instruction.Whenan

EXTESTinstructionisloadedintotheinstructionregister,

theSRAMrespondsasifaSAMPLE/PRELOADinstruction

hasbeenloaded.Thereisadifferencebetweentheinstruc-

tions, unlike the

SAMPLE/PRELOAD

instruction,EXTEST

placestheSRAMoutputsinaHigh-Zstate.

IDCODE

The IDCODE instruction causes a vendor-specic, 32-

bit code to be loaded into the instruction register. It also

placestheinstructionregisterbetweentheTDIandTDO

pins and allows the IDCODE to be shifted out of the device

when theTAP controller enters the Shift-DRstate.The

IDCODE instruction is loaded into the instruction register

uponpower-uporwhenevertheTAPcontrollerisgivena

test logic reset state.

SAMPLE-Z

The SAMPLE-Z instruction causes the boundary scan

whentheTAPcontrollerisinaShift-DRstate.Italsoplaces

allSRAMoutputsintoaHigh-Zstate.

SAMPLE/PRELOAD

SAMPLE/PRELOADisa1149.1mandatoryinstruction.The

PRELOADportionofthisinstructionisnotimplemented,so

theTAPcontrollerisnotfully1149.1compliant.Whenthe

SAMPLE/PRELOADinstructionisloadedtotheinstruc-

tionregisterandtheTAPcontrollerisintheCapture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

ItisimportanttorealizethattheTAPcontrollerclockoper-

atesatafrequencyupto10MHz,whiletheSRAMclock

runsmorethananorderofmagnitudefaster.Becauseof

the clock frequency differences, it is possible that during

theCapture-DRstate,aninputoroutputwillunder-goa

transition.TheTAPmayattemptasignalcapturewhilein

transition(metastablestate).Thedevicewillnotbeharmed,

but there is no guarantee of the value that will be captured

or repeatable results.

Toguaranteethattheboundaryscanregisterwillcapture

thecorrectsignalvalue,theSRAMsignalmustbestabilized

longenoughtomeettheTAPcontroller’scaptureset-up

plus hold times (tcS and tch).ToinsurethattheSRAMclock

input is captured correctly, designs need a way to stop (or

slow)theclockduringaSAMPLE/PRELOADinstruction.

If this is not an issue, it is possible to capture all other

signalsandsimplyignorethevalueoftheCLKcaptured

in the boundary scan register.

Once the data is captured, it is possible to shift out the data

byputtingtheTAPintotheShift-DRstate.Thisplacesthe

boundaryscanregisterbetweentheTDIandTDOpins.

Notethatsincethe

PRELOAD

part of the command is not

implemented, putting the

TA P

into the

Update

to the

Update-

state while performing a

SAMPLE/PRELOAD

instruction

willhavethesameeffectasthePause-DRcommand.

BYPASS

When the BYPASS instruction is loaded in the instruc-

tionregisterandtheTAP is placed in aShift-DRstate,

thebypassregisterisplacedbetweentheTDIandTDO

pins.TheadvantageoftheBYPASSinstructionisthatit

shortens the boundary scan path when multiple devices

are connected together on a board.

RESERVED

Theseinstructionsarenotimplementedbutarereserved

for future use. Do not use these instructions.

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