TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 28 November 2012 10 of 38
NXP Semiconductors
TJA1082
FlexRay node transceiver
6.2.2 Power-down
The behavior of the TJA1082 during power-down is illustrated in Figure 7.
Fig 6. Power-up behavior (example)
STBN
V
CC
V
IO
V
uvr(VCC)
V
th(rec)POR
V
uvr(VIO)
NormalStandbyPower-off
ERRN
RXD
015aaa005
Fig 7. Power-down behavior (example)
TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 28 November 2012 11 of 38
NXP Semiconductors
TJA1082
FlexRay node transceiver
6.3 Remote wake-up
6.3.1 Bus wake-up via wake-up pattern
A valid remote wake-up event occurs when a wake-up pattern is received. A wake-up
pattern consists of at least two consecutive wake-up symbols. A wake-up symbol consists
of a DATA_0 phase lasting longer than t
det(wake)DATA_0
, followed by an idle phase lasting
longer than t
det(wake)idle
, provided both wake-up symbols occur within a time span of
t
det(wake)tot
(see Figure 8). The transceiver also wakes up if the idle phases are replaced
by DATA_1 phases.
The wake-up mechanism of the TJA1082 follows the state transition diagram shown in
Figure 9
. See Ref. 1 for more details of the wake-up mechanism.
Fig 8. Bus wake-up timing
0
V
dif
(mV)
0
-500
> t
det(wake)DATA_0
> t
det(wake)idle
> t
det(wake)idle
> t
det(wake)DATA_0
> t
det(wake)DATA_0
> t
det(wake)DATA_0
> t
det(wake)idle
> t
det(wake)idle
wake-up
+500
015aaa007
0
-500
< t
det(wake)tot
wake-up pattern
wake-up symbol wake-up symbol
TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 28 November 2012 12 of 38
NXP Semiconductors
TJA1082
FlexRay node transceiver
6.3.2 Bus wake-up via dedicated FlexRay data frame
The TJA1082 wake flag is set when a dedicated data frame emulating a valid wake-up
pattern, as shown in Figure 10
, is received.
The DATA_0 and DATA_1 phases of the emulated wake-up symbol are interrupted by the
Byte Start Sequence (BSS) preceding each byte in the data frame. With a data rate of
10 Mbit/s, the interruption has a maximum duration of 130 ns and does not prevent the
transceiver from recognizing the wake-up pattern in the payload.
For longer interruptions at lower data rates (5 Mbit/s and 2.5 Mbit/s), the wake-up pattern
should be used (see Section 6.3.1
).
The wake flag is not set if an invalid wake-up pattern is received. See Ref. 1
for more
details on invalid wake-up patterns.
Fig 9. Wake-up state machine
Wait I'
DATA_1 or idle on bus
DATA_0 for longer than t
sup(int)wake
Initial state
start t
det(wake)idle
t
det(wake)idle
expired
Wait S'
Start state
Wait A'
Wait state A
start t
det(wake)Data_0
start t
det(wake)idle
Wait B'
Wait state B
start t
det(wake)Data_0
Wait C'
Wait state C
start t
det(wake)idle
DATA_0 on bus
DATA_1 or idle for longer than t
sup(int)wake
t
det(wake)Data_0
expired
DATA_1 or idle on bus
DATA_0 for longer than t
sup(int)wake
t
det(wake)idle
expired
DATA_0 on bus
DATA_1 or idle for longer than t
sup(int)wake
t
det(wake)Data_0
expired
DATA_1 or idle on bus
DATA_0 for longer than t
sup(int)wake
Wake-up!
t
det(idle)wake
expired
t
det(wake)tot
expired
t
det(wake)tot
expired
t
det(wake)tot
expired
t
det(wake)tot
expired
t
det(wake)tot
expired
t
det(wake)tot
expired
power on
015aaa008

TJA1082TT,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized IC TXRX FLEXRAY
Lifecycle:
New from this manufacturer.
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