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TJA1082TT,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 28 November 2012 16 of 38
NXP Semiconductors
TJA1082
FlexRay node transceiver
If a V
IO
undervoltage condition is detected, it is not possible to switch between SPI mode
and simple error indication mode.
6.8.1 SPI mode
The error flag information in the status register is latched in SPI mode. This means that
the status bit is reset once the status register has been completely read (provided the
corresponding error flag has been reset). If an error condition is detected in Normal mode,
pin ERRN goes LOW (provided one of the error bits, S5-S10, is set). Pin ERRN goes
HIGH again once all the error bits (S5-S10) have been reset.
6.8.2 Simple error indication mode
If an error condition is detected in Normal mode, pin ERRN goes LOW once the relevant
error flag has been set. Pin ERRN goes HIGH again when all error conditions have been
cleared and all flags have been reset. Error flags are not latched. It is not possible to
read-out the status bits in this mode.
6.9 SPI interface
The TJA1082 includes a 16-bit SPI interface to enable a host to read the status register
when the transceiver is in SPI mode (see Section 6.8
).
While pin SCSN is HIGH, the SDO output is in a high-impedance state. To begin a status
register readout, the host must force pin SCSN LOW. This causes the SDO pin to output a
LOW level by default. The data at pin SDO is then shifted out on the rising edge of the
clock signal on pin SCLK.
The status bits shifted out at SDO are active HIGH. The status bits are refreshed and pin
SDO returned to a high-impedance state once the status register has been read
successfully (after exactly 16 clock cycles) and SCSN has been forced HIGH again. Clock
signals on SCLK are ignored while SCSN is HIGH. The timing diagram for the SPI readout
is illustrated in Figure 12
.
The SLCK period ranges from 500 ns to 100 s (10 kbit/s to 2 Mbit/s).
Fig 11. Timing diagram for configuration of error indication mode
SCSN
(V)
0
V
IO
t
SCLK
(V)
0
V
IO
t
t
det(L)(SCLK)
SPI mode simple error
indication mode
SPI mode
015aaa015
TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 28 November 2012 17 of 38
NXP Semiconductors
TJA1082
FlexRay node transceiver
If SCSN remains LOW for longer than 16 clock cycles, it recognized as an SPI error.
When this happens, the SPI error flag is set and pin SDO goes to a high-impedance state
until the next falling edge on pin SCSN.
An SPI error is also assumed if fewer than 16 clock cycles are received while SCSN is
LOW. If this happens, the SPI error flag is set.
All status bits are refreshed once the status register has been successfully read.
When the transceiver is in simple error indication mode the SDO output is in a
high-impedance state and pin SCSN is in pull-down mode. In SPI mode pin SCSN is in
pull-up mode.
SPI readout is not possible when the transceiver has detected an undervoltage on V
IO
.
7. Limiting values
Fig 12. SPI readout timing diagram
SCSN
SCLK
SDO
Z L S0 S1 S2 S14 S15 Z
01 02 03 15 16
t
d(SCSNLH-SDOZ)
T
SCLK
t
d(SCLKLH-SDODV)
t
d(SCSNHL-SDOL)
015aaa009
t
SPILEAD
t
SPILAG
Table 9. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage no time limit 0.3 +5.5 V
V
IO
supply voltage on pin V
IO
no time limit 0.3 +5.5 V
V
ERRN
voltage on pin ERRN no time limit 0.3 V
IO
+ 0.3 V
V
RXD
voltage on pin RXD no time limit 0.3 V
IO
+ 0.3 V
V
SDO
voltage on pin SDO no time limit 0.3 V
IO
+ 0.3 V
V
TXEN
voltage on pin TXEN no time limit 0.3 +5.5 V
V
TXD
voltage on pin TXD no time limit 0.3 +5.5 V
V
STBN
voltage on pin STBN no time limit 0.3 +5.5 V
V
SCSN
voltage on pin SCSN no time limit 0.3 +5.5 V
V
SCLK
voltage on pin SCLK no time limit 0.3 +5.5 V
V
BGE
voltage on pin BGE no time limit 0.3 +5.5 V
V
BP
voltage on pin BP no time limit (with respect to pins BM
and GND)
60 +60 V
TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 28 November 2012 18 of 38
NXP Semiconductors
TJA1082
FlexRay node transceiver
[1] According to ISO7637, test pulse 1, class C; verified by an external test house.
[2] According to ISO7637, test pulse 2a, class C; verified by an external test house.
[3] According to ISO7637, test pulse 3a, class C; verified by an external test house.
[4] According to ISO7637, test pulse 3b, class C; verified by an external test house.
[5] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature T
vj
is: T
vj
= T
amb
+ TD x R
th(j-a)
, where R
th(j-a)
is
a fixed value to be used for the calculation of T
vj
. The rating for T
vj
limits the allowable combinations of power dissipation (P) and
ambient temperature (T
amb
).
[6] IEC61000-4-2: C = 150 pF; R = 330 .
[7] HBM: C = 100 pF; R = 1.5 k.
[8] MM: C = 200 pF; L = 0.75 H; R = 10 .
[9] CDM: R = 1 .
8. Thermal characteristics
V
BM
voltage on pin BM no time limit (with respect to pins BP
and GND)
60 +60 V
I
I(ERRN)
input current on pin ERRN no time limit; V
IO
=0V 10 10 mA
I
I(RXD)
input current on pin RXD no time limit; V
IO
=0V 10 10 mA
I
I(SDO)
input current on pin SDO no time limit; V
IO
=0V 10 10 mA
V
trt
transient voltage on pins BM and BP
[1]
100 - V
[2]
-75 V
[3]
150 - V
[4]
-100 V
T
stg
storage temperature 55 +150 C
T
vj
virtual junction temperature
[5]
40 +150 C
V
ESD
electrostatic discharge voltage IEC61000-4-2 on pins BP and BM to
ground
[6]
8.0 +8.0 kV
HBM on pins BP and BM to ground
[7]
8.0 +8.0 kV
HBM on any other pin
[7]
4.0 +4.0 kV
MM on all pins
[8]
200 +200 V
CDM on all pins
[9]
1000 +1000 V
Table 9. Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
Symbol Parameter Conditions Min Max Unit
Table 10. Thermal characteristics
Symbol Parameter Conditions Typ Unit
R
th(j-a)
thermal resistance from junction to ambient in free air 130 K/W
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

TJA1082TT,118

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Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized IC TXRX FLEXRAY
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