OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

5P49V5907B000NDGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
PROGRAMMABLE CLOCK GENERATOR 16 MARCH 3, 2017
5P49V5907 DATASHEET
Table 20: AC Timing Electrical Characteristics (V
DDO
= 1.8V ±5%, TA = -40°C to +85°C)
(Spread Spectrum Generation = OFF)
Symbol
Parameter Test Conditions
Min. Typ. Max. Units
Input frequency limit (XIN)
840MHz
Input frequency limit (REF)
1200MHz
Single ended clock output limit (LVCMOS)
1200
Differential clock output limit 1 350
f
VCO
VCO Frequency
VCO operating frequency range
2500 2900 MHz
f
PFD
PFD Frequency
PFD operating frequency range 1
1
150 MHz
f
BW
Loop Bandwidth Input frequency = 25MHz 0.06 0.9 MHz
t2 Input Duty Cycle
Duty Cycle
45 55 %
Measured at VDD/2, all outputs except
Reference output OUT0, VDDOX= 2.5V or
3.3V
45 50 55 %
Measured at VDD/2, all outputs except
Reference output OUT0, VDDOX=1.8V
40 50 60 %
Measured at VDD/2, Reference output
OUT0 (5MHz - 120MHz) with 50% duty
cycle input
40 50 60 %
Measured at VDD/2, Reference output
OUT0 (150.1MHz - 200MHz) with 50% duty
cycle input
30 50 70 %
Slew Rate, SLEW[1:0] = 00
1.0
2.2
Slew Rate, SLEW[1:0] = 01
1.2
2.3
Slew Rate, SLEW[1:0] = 10
1.3
2.4
Slew Rate, SLEW[1:0] = 11
1.7
2.7
Slew Rate, SLEW[1:0] = 00
0.6
1.3
Slew Rate, SLEW[1:0] = 01
0.7
1.4
Slew Rate, SLEW[1:0] = 10
0.6
1.4
Slew Rate, SLEW[1:0] = 11
1.0
1.7
Slew Rate, SLEW[1:0] = 00
0.3
0.7
Slew Rate, SLEW[1:0] = 01
0.4
0.8
Slew Rate, SLEW[1:0] = 10
0.4
0.9
Slew Rate, SLEW[1:0] = 11
0.7
1.2
Rise Times
LVDS, 20% to 80%
300
Fall Times
LVDS, 80% to 20%
300
Rise Times
LVPECL, 20% to 80%
400
Fall Times
LVPECL, 80% to 20%
400
V/ns
Single-ended 2.5V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=2.5V
Single-ended 1.8V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=1.8V
t5 ps
f
IN
1
Input Frequency
f
OUT
Output Frequency MHz
t3
5
Output Duty Cycle
t4
2
Single-ended 3.3V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=3.3V
MARCH 3, 2017 17 PROGRAMMABLE CLOCK GENERATOR
5P49V5907 DATASHEET
Table 21: PCI Express Jitter Specifications (V
DDO
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to +85°C)
(For regular HCSL (OUT1, OUT2 and OUT4) outputs)
Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained
transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.
1. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1.
2. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation
band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t
REFCLK_HF_RMS
(High Band) and 3.0ps RMS for t
REFCLK_LF_RMS
(Low Band).
3. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI_Express_Base_r3.0 10 Nov, 2010 specification, and is
subject to change pending the final release version of the specification.
4. This parameter is guaranteed by characterization. Not tested in production.
Cycle-to-Cycle jitter (Peak-to-Peak),
multiple output frequencies switching,
differential outputs
46 ps
Cycle-to-Cycle jitter (Peak-to-Peak),
multiple output frequencies switching,
LVCMOS outputs
74 ps
RMS Phase Jitter (12kHz to 5MHz
integration range) reference clock (OUT0),
25 MHz LVCMOS outputs
0.5 ps
RMS Phase Jitter (12kHz to 20MHz
integration range) differential output, 25MHz
crystal, 156.25MHz output frequency
0.75 1.5 ps
Output Skew between OUT1,
OUT2, OUT4
Skew between the same frequencies , with
outputs using the same driver format and
phase delay set to 0 ns.
75 ps
Output Skew between OUT3
and OUT5-11
Skew between outputs at same frequency
and conditions
49.5 84 ps
t8
3
Startup Time
PLL lock time from power-up, measured
after all VDD's have raised above 90% of
their target value.
10 ms
t9
4
Startup Time PLL lock time from shutdown mode
2ms
5. Duty Cycle is only guaranteed at max slew rate settings.
3. Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/w rite time.
4. Actual PLL lock time depends on the loop configuration.
t6 Clock Jitter
t7
1. Practical low er frequency is determined by loop filter settings.
2. A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
Symbol Parameter Conditions Min Typ Max
PCIe Industry
Specification
Units Notes
t
J
(PCIe Gen1)
Phase Jitter Peak-
to-Peak
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist (clock
frequency/2)
30 86 ps 1,4
t
REFCLK_HF_RMS
(PCIe Gen2)
Phase Jitter RMS
ƒ = 100MHz, 25MHz Crystal Input High
Band: 1.5MHz - Nyquist (clock
frequency/2)
2.56 3.10 ps 2,4
t
REFCLK_LF_RMS
(PCIe Gen2)
Phase Jitter RMS
ƒ = 100MHz, 25MHz Crystal Input Low
Band: 10kHz - 1.5MHz
0.27 3.0 ps 2,4
t
REFCLK_RMS
(PCIe Gen3)
Phase Jitter RMS
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist (clock
frequency/2)
0.8 1.0 ps 3,4
PROGRAMMABLE CLOCK GENERATOR 18 MARCH 3, 2017
5P49V5907 DATASHEET
Table 22: PCI Express Jitter Specifications (V
DDO
= 1.8V +5%, T
A
= -40°C to +85°C)
(For LP-HCSL (OUT3, OUT5-7) outputs.)
Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained
transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.
1. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1.
2. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation
band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t
REFCLK_HF_RMS
(High Band) and 3.0ps RMS for t
REFCLK_LF_RMS
(Low Band).
3. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI_Express_Base_r3.0 10 Nov, 2010 specification, and is
subject to change pending the final release version of the specification.
4. This parameter is guaranteed by characterization. Not tested in production.
Table 23: Spread Spectrum Generation Specifications
Symbol Parameter Conditions Min Typ Max
PCIe Industry
Specification
Units Notes
t
J
(PCIe Gen1)
Phase Jitter Peak-
to-Peak
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist (clock
frequency/2)
23.85 86 ps 1,4
t
REFCLK_HF_RMS
(PCIe Gen2)
Phase Jitter RMS
ƒ = 100MHz, 25MHz Crystal Input High
Band: 1.5MHz - Nyquist (clock
frequency/2)
1.83 3.1 ps 2,4
t
REFCLK_LF_RMS
(PCIe Gen2)
Phase Jitter RMS
ƒ = 100MHz, 25MHz Crystal Input Low
Band: 10kHz - 1.5MHz
0.54 3 ps 2,4
t
REFCLK_RMS
(PCIe Gen3)
Phase Jitter RMS
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist (clock
frequency/2)
0.51 1 ps 3,4
Symbol Parameter Description Min Typ Max Unit
f
OUT
Output Frequency
Output Frequency Range 1 300 MHz
f
MOD
Mod Frequency
Modulation Frequency kHz
Amount of Spread Value (programmable) - Center Spread
Amount of Spread Value (programmable) - Down Spread
±0.25% to ±2.5%
-0.5% to -5%
30 to 63
f
SPREAD
Spread Value
%f
OUT
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

5P49V5907B000NDGI

Mfr. #:
Buy 5P49V5907B000NDGI
Manufacturer:
IDT
Description:
Clock Generators & Support Products XTAL 1 LVCMOS PCIe 4 Out 7 Diff 3 Pairs
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet