PROGRAMMABLE CLOCK GENERATOR 6 MARCH 3, 2017
5P49V5907 DATASHEET
OTP Interface
The 5P49V5907 can also store its configuration in an internal
OTP. The contents of the device's internal programming
registers can be saved to the OTP by setting burn_start
(W114[3]) to high and can be loaded back to the internal
programming registers by setting usr_rd_start(W114[0]) to
high.
To initiate a save or restore using I
2
C, only two bytes are
transferred. The Device Address is issued with the read/write
bit set to “0”, followed by the appropriate command code. The
save or restore instruction executes after the STOP condition
is issued by the Master, during which time the 5P49V5907 will
not generate Acknowledge bits. The 5P49V5907 will
acknowledge the instructions after it has completed execution
of them. During that time, the I
2
C bus should be interpreted as
busy by all other users of the bus.
On power-up of the 5P49V5907, an automatic restore is
performed to load the OTP contents into the internal
programming registers. The 5P49V5907 will be ready to
accept a programming instruction once it acknowledges its
7-bit I
2
C address.
Availability of Primary and Secondary I
2
C addresses to allow
programming for multiple devices in a system. The I
2
C slave
address can be changed from the default 0xD4 to 0xD0 by
programming the I2C_ADDR bit D0. VersaClock 5
Programming Guide provides detailed I
2
C programming
guidelines and register map.
SD/OE Pin Function
The polarity of the SD/OE signal pin can be programmed to be
either active HIGH or LOW with the SP bit (W16[1]). When SP
is “0” (default), the pin becomes active LOW and when SP is
“1”, the pin becomes active HIGH. The SD/OE pin can be
configured as either to shutdown the PLL or to enable/disable
the outputs. The SH bit controls the configuration of the
SD/OE pin The SH bit needs to be high for SD/OE pin to be
configured as SD
.
When configured as SD, device is shut down, differential
outputs are driven High/low, and the single-ended LVCMOS
outputs are driven low. When configured as OE, and outputs
are disabled, the outputs are driven high/low.
Table 4: SD/OE Pin Function Truth Table
Output Alignment
Each output divider block has a synchronizing POR pulse to
provide startup alignment between outputs. This allows
alignment of outputs for low skew performance. The phase
alignment works both for integer output divider values and for
fractional output divider values.
Besides the POR at power up, the same synchronization reset
is also triggered when switching between configurations with
the SEL0/1 pins. This ensures that the outputs remain aligned
in every configuration. This reset causes the outputs to
suspend for a few hundred microseconds so the switchover is
not glitch-less. The reset can be disabled for applications
where glitch-less switch over is required and alignment is not
critical.
When using I
2
C to reprogram an output divider during
operation, alignment can be lost. Alignment can be restored
by manually triggering the reset through I
2
C.
When alignment is required for outputs with different
frequencies, the outputs are actually aligned on the falling
edges of each output by default. Rising edge alignment can
also be achieved by utilizing the programmable skew feature
to delay the faster clock by 180 degrees. The programmable
skew feature also allows for fine tuning of the alignment.
For details of register programming, please see VersaClock 5
Family Register Descriptions and Programming Guide for
details.
SD/OE Input
SP
SH
OEn
OSn
Global Shutdown
OUTn
SH bit SP bit OSn bit OEn bit SD/OE OUTn
0 0 0 x x Tri-state
2
0 0 1 0 x Output active
0 0 1 1 0 Output active
0 0 1 1 1 Output driven High Low
0 1 0 x x Tri-state
2
0 1 1 0 x Output active
0 1 1 1 0 Output driven High Low
0 1 1 1 1 Output active
1 0 0 x 0 Tri-state
2
1 0 1 0 0 Output active
1 0 1 1 0 Output active
1 1 0 x 0 Tri-state
2
1 1 1 0 0 Output active
1 1 1 1 0 Output driven High Low
1x x x 1
Output driven High Low
1
Note 1 : Global Shutdown
Note 2 : Tri-state regardless of OEn bits
