MARCH 3, 2017 7 PROGRAMMABLE CLOCK GENERATOR
5P49V5907 DATASHEET
Output Divides
Each of the four output divides are comprised of a 12-bit
integer counter, and a 24-bit fractional counter. The output
divide can operate in integer divide only mode for improved
performance, or utilize the fractional counters to generate any
frequency with a synthesis accuracy better than 50ppb.
The Output Divide also has the capability to apply a spread
modulation to the output frequency. Independent of output
frequency, a triangle wave modulation between 30 and 63kHz
may be generated.
Output Skew
For outputs that share a common output divide value, there
will be the ability to skew outputs by quadrature values to
minimize interaction on the PCB. The skew on each output
can be adjusted from 0 to 360 degrees. Skew is adjusted in
units equal to 1/32 of the VCO period. So, for 100 MHz output
and a 2800 MHz VCO, you can select how many 11.161pS
units you want added to your skew (resulting in units of 0.402
degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and so
on. The granularity of the skew adjustment is always
dependent on the VCO period and the output period.
Output Drivers
The OUT1 to OUT4 clock outputs are provided with
register-controlled output drivers. By selecting the output drive
type in the appropriate register, any of these outputs can
support LVCMOS, LVPECL, HCSL or LVDS logic levels
The operating voltage ranges of each output is determined by
its independent output power pin (V
DDO
) and thus each can
have different output voltage levels. Output voltage levels of
2.5V or 3.3V are supported for differential HCSL, LVPECL
operation, and 1. 8V, 2.5V, or 3.3V are supported for LVCMOS
and differential LVDS operation.
Each output may be enabled or disabled by register bits.
When disabled an output will be in a logic 0 state as
determined by the programming bit table shown on page 6.
LVCMOS Operation
When a given output is configured to provide LVCMOS levels,
then both the OUTx and OUTxB outputs will toggle at the
selected output frequency. All the previously described
configuration and control apply equally to both outputs.
Frequency, phase alignment, voltage levels and enable /
disable status apply to both the OUTx and OUTxB pins. The
OUTx and OUTxB outputs can be selected to be
phase-aligned with each other or inverted relative to one
another by register programming bits. Selection of
phase-alignment may have negative effects on the phase
noise performance of any part of the device due to increased
simultaneous switching noise within the device.
Device Start-up & Reset Behavior
The 5P49V5907 has an internal power-up reset (POR) circuit.
The POR circuit will remain active for a maximum of 10ms
after device power-up.
Upon internal POR circuit expiring, the device will exit reset
and begin self-configuration.
The device will load internal registers using the configuration
stored in the internal One-Time Programmable (OTP)
memory.
Once the full configuration has been loaded, the device will
respond to accesses on the serial port and will attempt to lock
the PLL to the selected source and begin operation.
Power Up Ramp Sequence
VDDA and VDD must ramp up together. VDD0-1, VDDO4,
VDD_CORE and VDDO must ramp up before, or concurrently
with, VDDA and VDD. All power supply pins must be
connected to a power rail even if the output is unused. All
power supplies must ramp in a linear fashion and ramp
monotonically.
VDD0-1, VDDO4,
VDD_CORE and VDDO
VDD
