FTG for Pentium 4
®
and Intel
®
845 Series Chipset
CY28378
........................ Document #: 38-07519 Rev. ** Page 1 of 21
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com
Features
•Compatible with Intel
®
CK-Titan and CK-408 Clock
Synthesizer/Driver specifications
System frequency synthesizer for Intel Brookdale 845
and Brookdale – G Pentium 4
®
chipsets
Programmable clock output frequency with less than
1-MHz increment
Integrated fail-safe Watchdog timer for system
recovery
Automatically switch to HW selected or SW
programmed clock frequency when Watchdog timer
time-out
Programmable 3V66 and PCI output frequency mode
Capable of generating system RESET after a Watchdog
timer time-out or a change in output frequency via
SMBus interface occurs
Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
Vendor ID and Revision ID support
Programmable drive strength support
Programmable output skew support
Power management control inputs
Available in 48-pin SSOP
Table 1. Frequency Table
CPU 3V66 PCI REF 48M 24_48M
x 3 x 4 x 10 x 2 x 1 x 1
Note:
1. Signals marked with ‘*’ and ‘**’ have internal pull-up and pull-down resistors, respectively.
~
Block Diagram
VDD_REF
CPUT[0:1], CPUC[0:1],
XTAL
PLL Ref Freq
X2
X1
VDD_PCI
OSC
SCLK
PLL 1
SMBus
Logic
VDD_48MHz
SDATA
VDD_3V66
Divider
Network
VDD_CPU
*FS0:4
2
PWRDWN#
SSOP-48
REF0:1
VTT_PWRGD#
*MULTSEL1/REF1
VDD_REF
X1
X2
GND_PCI
*FS2/PCI_F0
*FS3/PCI_F1
PCI_F2
VDD_PCI
*FS4/PCI0
PCI1
PCI2
GND_PCI
PCI3
PCI4
PCI5
PCI6
VDD_PCI
VTT_PWRGD#
RESET#
GND_48MHz
*FS0/48MHz_0
*FS1/24_48MHz
VDD_48MHz
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
27
26
25
32
31
30
29
REF0/MULTSEL0**
GND_REF
VDD_CPU
CPU_ITP
CPU_ITP#
GND_CPU
PWRDWN#*
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
GNDC_CPU
IREF
VDD_CORE
GND_CORE
VDD_3V66
3V66_0
3V66_1
GND_3V66
3V66_2
3V66_3/48MHz_1
SCLK
SDATA
CY28378
*MULTSEL0:1
3V66_0:2
PCI_F0:2
PCI0:6
48MHz_0
24_48MHz
RESET#
CPU_ITP, CPU_ITP#
VDD_48MHz
3V66_3/48MHz_1
2
Fract.
Aligner
PLL2
Pin Configuration
[1]
CY28378
........................Document #: 38-07519 Rev. ** Page 2 of 21
Pin Description
Pin # Name Type Description
3X1 ICrystal Connection or External Reference Frequency Input: This
pin has dual functions. It can be used as an external 14.318-MHz
crystal connection or as an external reference frequency input.
4X2 OCrystal Connection: Connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
48 REF0/MULTSEL0 I/O Reference Clock 0/Current Multiplier Selection 0: 3.3V 14.318-MHz
clock output. This pin also serves as a power-on strap option to
determine the current multiplier for the CPU clock outputs. The
MULTSEL1:0 definitions are as follows:
MULTSEL1:0
00 = Ioh is 4 x IREF
01 = Ioh is 5 x IREF
10 = Ioh is 6 x IREF
11 = Ioh is 7 x IREF
150k internal pull down.
1 REF1/MULTSEL1 I/O Reference Clock 1/Current Multiplier Selection 1: 3.3V 14.318-MHz
clock output. This pin also serves as a power-on strap option to
determine the current multiplier for the CPU clock outputs. The
MULTSEL1:0 definitions are as follows:
MULTSEL1:0
00 = Ioh is 4 x IREF
01 = Ioh is 5 x IREF
10 = Ioh is 6 x IREF
11 = Ioh is 7 x IREF
150k internal pull up.
41, 38, 40, 37 CPUT(0:1),
CPUC(0:1)
O CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through
serial input interface.
44, 45 CPU_ITP,
CPU_ITP#
O CPU Clock Output for ITP: Frequency is set by the FS0:4 inputs or
through serial input interface.
31, 30, 28 3V66_0:2 O 66MHz Clock Outputs: 3.3V fixed 66-MHz clock.
6 PCI_F0/FS2 I/O Free-running PCI Output 0/Frequency Select 2: 3.3V free-running
PCI output. This pin also serves as a power-on strap option to
determine device operating frequency as described in the Frequency
Selection Table. 150k internal pull up.
7 PCI_F1/FS3 I/O Free-running PCI Output 1/Frequency Select 3: 3.3V free-running
PCI output. This pin also serves as a power-on strap option to
determine device operating frequency as described in the Table 2.
150k internal pull up.
8PCI_F2OFree-running PCI Output 2: 3.3V free-running PCI output.
10 PCI0/FS4 I/O PCI Output 0/Frequency Select 4: 3.3V PCI output. This pin also
serves as a power-on strap option to determine device operating
frequency as described in Table 2. 150k internal pull up.
11, 12, 14, 15, 16,
17
PCI(1:6) O PCI Clock Output 1 to 6: 3.3V PCI clock outputs.
22 48MHz_0/FS0 I/O 48MHz Output/Frequency Select 0: 3.3V fixed 48-MHz, non-spread
spectrum output. This pin also serves as a power-on strap option to
determine device operating frequency as described in Table 2.
This output will be used as the reference clock for USB host controller
in Intel 845 (Brookdale) platforms. For Intel Brookdale – G platforms,
this output will be used as the VCH reference clock. 150k internal pull
up.
CY28378
........................Document #: 38-07519 Rev. ** Page 3 of 21
23 24_48MHz/FS1 I/O 24 or 48MHz Output/Frequency Select 1: 3.3V fixed 24-MHz or
48-MHz non-spread spectrum output. This pin also serves as a
power-on strap option to determine device operating frequency as
described in Table 2. This output will be used as the reference clock
for SIO devices in Intel 845 (Brookdale) platforms. For Intel Brookdale
– G platforms, this output will be used as the reference clock for both
USB host controller and SIO devices. We recommend system designer
to configure this output as 48 MHz and “HIGH Drive” by setting Byte
[5], Bit [0] and Byte [9], Bit [7], respectively.150k internal pull up.
27 3V66_3/48MHz_1 O 48MHz or 66MHz Output: 3.3V output.
42 PWRDWN# I Power Down Control: 3.3V LVTTL compatible input that places the
device in power down mode when held low. 150k internal pull up.
26 SCLK I SMBus Clock Input: Clock pin for serial interface.
25 SDATA I/O SMBus Data Input: Data pin for serial interface.
20 RESET# O (open-drain) System Reset Output: Open-drain system reset output.
35 IREF I Current Reference for CPU Output: A precision resistor is attached
to this pin which is connected to the internal current reference.
19 VTT_PWRGD# I Powergood from Voltage Regulator Module (VRM): 3.3V LVTTL
input. VTT_PWRGD# is a level sensitive strobe used to determine
when FS0:4 and MULTSEL0:1 inputs are valid and OK to be sampled
(Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this
input will be ignored.
2, 9, 18, 24, 32, 39,
46
VDD_REF,
VDD _PCI,
VDD_48MHz,
VDD_3V66,
VDD_CPU
P 3.3V Power Connection: Power supply for CPU outputs buffers, 3V66
output buffers, PCI output buffers, reference output buffers and
48-MHz output buffers. Connect to 3.3V.
5, 13, 21, 29, 36,
43, 47
GND_PCI,
GND_48MHz,
GND_3V66,
GND_CPU,
GND_REF,
G Ground Connection: Connect all ground pins to the common system
ground plane.
34 VDD_CORE P 3.3V Analog Power Connection: Power supply for core logic, PLL
circuitry. Connect to 3.3V.
33 GND_CORE G Analog Ground Connection: Ground for core logic, PLL circuitry.
Pin Description
Pin # Name Type Description

CY28378OXC

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products System Clock for Pentium 4 and Intel Brookdale, 845 Chipsets
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet