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CY28378OXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
CY28378
......................Document #: 38-07519 Rev. ** Page 10 of 21
Watchdog Self Recovery Sequence
This feature is designed to allow the system designer to
change frequency while the system is running and reboot the
operation of the system in case of a hang up due to the
frequency change.
When the system sends an SMBus command requesting a
frequency change through the Dial-a-Frequency Control
Registers, it must have previously sent a command to the
Watchdog Timer to select which time out stamp the Watchdog
must perform, otherwise the System Self Recovery feature will
not be applicable. Consequently, this device will change
frequency and then the Watchdog timer starts timing.
Meanwhile, the system BIOS is running its operation with the
new frequency. If this device receives a new SMBus command
to clear the bits originally programmed in the Watchdog Timer
bits (reprogram to 0000) before the Watchdog times out, then
this device will keep operating in its normal condition with the
new selected frequency.
The Watchdog timer will also be triggered if you program the
software frequency select bits (FSEL) to a new frequency
selection. If the Watchdog times out before the new SMBus
reprograms the Watchdog Timer bits to (0000), then this
device will send a low system reset pulse, on SRESET# and
changes WD Time-out bit to “1.”
Byte 12
Bit @Pup Name Pin Description
Bit 7 0 Reserved Reserved
Bit 6 0 Reserved Reserved
Bit 5 0 Reserved Reserved
Bit 4 0 Reserved Reserved
Bit 3 0 Reserved Reserved
Bit 2 0 Reserved Reserved
Bit 1 0 Reserved Reserved
Bit 0 0 Reserved Reserved
Byte 13
Bit @Pup Name Pin Description
Bit 7 0 Reserved If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[6:0] and
CPU_FSEL_M[5:0] will be used to determine the CPU output frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[4:0] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
Bit 6 0 CPU_FSEL_N6
Bit 5 0 CPU_FSEL_N5
Bit 4 0 CPU_FSEL_N4
Bit 3 0 CPU_FSEL_N3
Bit 2 0 CPU_FSEL_N2
Bit 1 0 CPU_FSEL_N1
Bit 0 0 CPU_FSEL_N0
Byte 14
Bit @Pup Name Pin Description
Bit 7 0 Pro_Freq_EN Programmable output frequencies enabled
0 = disabled
1 = enabled
Bit 6 0 Reserved Reserved
Bit 5 0 CPU_FSEL_M5 If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[6:0] and
CPU_FSEL_M[5:0] will be used to determine the CPU output frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[4:0] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
Bit 4 0 CPU_FSEL_M4
Bit 3 0 CPU_FSEL_M3
Bit 2 0 CPU_FSEL_M2
Bit 1 0 CPU_FSEL_M1
Bit 0 0 CPU_FSEL_M0
CY28378
......................Document #: 38-07519 Rev. ** Page 11 of 21
Program the CPU output frequency
When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is deter-
mined by the following equation:
Fcpu = G * N/M.
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
“G” stands for the PLL Gear Constant, which is determined by
the programmed value of FS[4:0] or SEL[4:0]. The value is
listed in Table 2.
The ratio of N and M need to be greater than “1” [N/M> 1].
The following table lists set of N and M values for different
frequency output ranges. This example use a fixed value for
the M-Value Register and select the CPU output frequency by
changing the value of the N-Value Register.
RESET W ATCHDOG TIMER
Set WD(0:3) Bits = 0
INITIALIZE W ATCHDOG TIMER
Set Frequency Revert Bit
Set WD(0:3) = (# of Sec ) x 2
SET SOFTW ARE FSEL
Set SW Freq_Sel = 1
Set FS(0:4)
Wait for 6msec For
Clock Output to Ramp to
Target Frequency
Hang?
Y
WATCHDOG TIMEOUT
N CLEAR WD
Set WD(0:3) Bits = 0
Exit
Reset
Frequency Revert Bit =
0
Set Frequency to
FS_HW_Latched
Frequency Revert Bit =
1
Set Frequency to FS_SW
Set SRESET# = 0 for 6 msec
SET DIAL-A-FREQUENCY
Load M and N Registers
Set Pro_Freq_EN = 1
Table 6. Examples of N and M Value for Different CPU Frequency Range
Frequency Ranges Gear Constants Fixed Value for M-Value Register
Range of N-Value Register for Different
CPU Frequency
66 – 127 47.99750 48 66 – 127
128 – 203 63.99667 40 80 – 127
CY28378
......................Document #: 38-07519 Rev. ** Page 12 of 21
PD# (Power-down) Clarification
The PD# (Power Down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is low, all clocks are driven to a LOW value and held there and
the VCO and PLLs are also powered down. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the low “stopped” state.
PD# – Assertion
Table 7. Maximum Lumped Capacitive Output Loads
Clock Max Load Units
PCI, PCI_F 20 pF
3V66 30 pF
48M_24MHz, 48MHz 20 pF
REF 30 pF
CPUT/C
CPU_ITP
See Figure 4 pF
Table 8. Group Timing Relationship and Tolerances
Offset
Tolerance
(or Range) Conditions Notes
3V66 to PCI Typical 2.5 ns 1.5 – 3.5 ns 3V66 leads See Note 2
PWRDWN#
AGP, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.131818
CPUC, 133MHz
CPUT, 133MHz
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

CY28378OXC

Mfr. #:
Buy CY28378OXC
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products System Clock for Pentium 4 and Intel Brookdale, 845 Chipsets
Lifecycle:
New from this manufacturer.
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