CY28378OXC Datasheet CY28378OXC, CY28378OXCT | P16-P18

CY28378

......................Document #: 38-07519 Rev. ** Page 16 of 21

Test and Measurement Set-up

For Differential CPU Output Signals

The following diagram shows lumped test load configurations

for the differential Host Clock Outputs.

CPUT

MULTSEL

PCB

CPUC





Measurement Point

2pF



IREF

Measurement Point

2pF

Figure 4. 0.7V Configuration

2.4V

0.4V

3.3V

Tr Tf

1.5V

3.3V signals

tDC

Probe

Output under Test

Load Cap

Figure 5. Lumped Load For Single-Ended Output Signals (for AC Parameters Measurement)

CY28378

......................Document #: 38-07519 Rev. ** Page 17 of 21

Switching Waveforms

Note:

6. Device is not affected, VTT_PWRGD# is ignored.

FS_A, FS_B

VTT_PWRGD#

PWRGD_VRM

VDD Clock Gen

Clock State

Clock Outputs

Clock VCO

0.2-0.3mS

Delay

State 0

State 2 State 3

Wait for

VTT_PWRGD#

Sample Sels

Off

State 1

Device is not affected,

VTT_PWRGD# is ignored

Figure 6. VTT_PWRGD# Timing Diagram

[6]

VTT_PWRGD# = Low

Delay

>0.25mS

Power Off

VDDA = 2.0V

Sample

Inputs straps

Normal

Operation

Wait for 1.146ms

Enable Outputs

VTT_PWRGD# = toggle

VDDA = off

Figure 7. Clock Generator Power-up/Run State Diagram

Duty Cycle Timing

(Single-ended Output)

CY28378

......................Document #: 38-07519 Rev. ** Page 18 of 21

Switching Waveforms (continued)

Duty Cycle Timing (CPU Differential Output)

All Outputs Rise/Fall Time

OUTPUT

CPU-CPU Clock Skew

Host_b

Host

Host_b

Host

3V66-3V66 Clock Skew

3V66

PCI-PCI Clock Skew

PCI

3V66

PCI

3V66-PCI Clock Skew

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

CY28378OXC

Mfr. #:

Buy CY28378OXC

Manufacturer:

Silicon Labs

Description:

Clock Generators & Support Products System Clock for Pentium 4 and Intel Brookdale, 845 Chipsets

Lifecycle:

New from this manufacturer.

Delivery:

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CY28378OXC

CY28378OXC

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