CY28378
........................Document #: 38-07519 Rev. ** Page 7 of 21
Byte 2
Bit @pup Name Pin Description
Bit 7 0 Reserved Reserved
Bit 6 1 PCI6 (Active/Inactive)
Bit 5 1 PCI5 (Active/Inactive)
Bit 4 1 PCI4 (Active/Inactive)
Bit 3 1 PCI3 (Active/Inactive)
Bit 2 1 PCI2 (Active/Inactive)
Bit 1 1 PCI1 (Active/Inactive)
Bit 0 1 PCI0 (Active/Inactive)
Byte 3
Bit @Pup Name Pin Description
Bit 7 1 PCI_F2 (Active/Inactive)
Bit 6 1 PCI_F1 (Active/Inactive)
Bit 5 1 PCI_F0 (Active/Inactive)
Bit 4 0 Reserved Reserved
Bit 3 1 CPU_ITP, CPU_ITP# (Active/Inactive)
Bit 2 0 Reserved Reserved
Bit 1 1 REF1 (Active/Inactive)
Bit 0 1 REF0 (Active/Inactive)
Byte 4
Bit @Pup Name Pin Description
Bit 7 0 MULTSEL_Override This bit control the selection of IREF multiple.
0 = HW control; IREF multiplier is determined by MULTSEL[0:1] input pins
1 = SW control; IREF multiplier is determined by Byte[4], Bit[5:6].
Bit 6 HW SW_MULTSEL1 IREF multiplier
00 = Ioh is 4 x IREF
01 = Ioh is 5 x IREF
10 = Ioh is 6 x IREF
11 = Ioh is 7 x IREF
Bit 5 HW SW_MULTSEL0
Bit 4 0 Reserved Reserved
Bit 3 0 Reserved Reserved
Bit 2 0 Reserved Reserved
Bit 1 0 Reserved Reserved
Bit 0 0 Reserved Vendor Test Mode (always program to 0)
Byte 5
Bit @Pup Name Pin Description
Bit 7 HW Latched FS4 input Latched FS[4:0] inputs. These bits are read only.
Bit 6 HW Latched FS3 input
Bit 5 HW Latched FS2 input
Bit 4 HW Latched FS1 input
Bit 3 HW Latched FS0 input
Bit 2 0 FS_Override 0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
Bit 1 0 SEL 3V66 0 = 48-MHz output on pin 27, 1 = 66-MHz output on pin 27
Bit 0 1 SEL 48MHZ 0 = 24-MHz,1 = 48-MHz
CY28378
........................Document #: 38-07519 Rev. ** Page 8 of 21
Byte 6
Bit @Pup Name Pin Description
Bit 7 0 Revision_ID3 Revision ID bit[3]
Bit 6 0 Revision_ID2 Revision ID bit[2]
Bit 5 0 Revision_ID1 Revision ID bit[1]
Bit 4 1 Revision_ID0 Revision ID bit[0]
Bit 3 1 Vendor_ID3 Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 2 0 Vendor_ID2 Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 1 0 Vendor _ID1 Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 0 0 Vendor _ID0 Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Byte 7
Bit @Pup Name Pin Description
Bit 7 0 Reserved Vendor Test Mode (always program to 0)
Bit 6 0 Reserved Vendor Test Mode (always program to 0)
Bit 5 0 Reserved Vendor Test Mode (always program to 0)
Bit 4 0 Reserved Vendor Test Mode (always program to 0)
Bit 3 0 3V66 Fract_Align3 3V66 Frequency Fractional Aligner: These bits determine the 3V66 fixed frequency. This
option does not incorporate spread spectrum and is enabled through Byte10, bit 4
Bit 2 0 3V66 Fract_Align2
Bit 1 0 3V66 Fract_Align1
Bit 0 0 3V66 Fract_Align0
Byte 8
Bit @Pup Name Pin Description
Bit 7 0 WD_Alarm This bit is set to “1” when the Watchdog times out. It is reset to “0” when
the system clears the WD_TIMER time stamp
Bit 6 0 Frequency_Revert This bit allows setting the Revert Frequency once the system is rebooted
0: Hardware
1: Last Programmed
Bit 5 0 Reserved Reserved
Bit 4 0 WD_TIMER3 Watchdog timer time stamp selection:
0000: Off
0001: 1 second
0010: 2 seconds
.
.
.
1110: 14 seconds
1111: 15 seconds
Bit 3 0 WD_TIMER2
Bit 2 0 WD_TIMER1
Bit 1 0 WD_TIMER0
Bit 0 1 Reserved Reserved
000166.533.2
001067.533.7
001168.534.3
010069.534.8
010170.635.3
011071.635.8
011172.636.3
100073.636.8
100174.737.3
101075.737.8
101176.738.4
110077.738.9
CY28378
........................Document #: 38-07519 Rev. ** Page 9 of 21
Byte 9
Bit @Pup Name Pin Description
Bit 7 0 48MHz_DRV 48MHz and 24_48MHz clock output drive strength
0 = Normal
1 = High Drive
(Recommend to set to high drive if this output is being used to drive both
USB and SIO devices in Intel Brookdale – G platforms)
Bit 6 0 PCI_DRV PCI clock output drive strength
0 = Normal
1 = High Drive
Bit 5 0 3V66_DRV 3V66 clock output drive strength
0 = Normal
1 = High Drive
Bit 4 0 Reserved Reserved
Bit 3 0 Reserved Reserved
Bit 2 0 Reserved Reserved
Bit 1 0 Reserved Reserved
Bit 0 0 Reserved Reserved
Byte 10
Bit @Pup Name Pin Description
Bit 7 0 CPU_Skew2 CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Bit 6 0 CPU_Skew1
Bit 5 0 CPU_Skew0
Bit 4 0 Fixed 3V66_SEL 3V66 and PCI output frequency select mode
0 = Set according to Frequency Selection Table
1 = Set according to Fractional Aligner settings
Bit 3 0 PCI_Skew1 PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
Bit 2 0 PCI_Skew0
Bit 1 0 3V66_Skew1 3V66 skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Bit 0 0 3V66_Skew0
Byte 11
Bit @Pup Name Pin Description
Bit 7 0 Reserved Reserved
Bit 6 0 Reserved Reserved
Bit 5 0 Reserved Reserved
Bit 4 0 Reserved Reserved
Bit 3 0 Reserved Reserved
Bit 2 0 Reserved Reserved
Bit 1 0 Reserved Reserved
Bit 0 0 Reserved Reserved

CY28378OXC

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products System Clock for Pentium 4 and Intel Brookdale, 845 Chipsets
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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