Si4114G
14 Rev. 1.1
3. Functional Description
The Si4114G is a monolithic integrated circuit (IC) that
performs multi-band RF synthesis for E-GSM 900,
DCS 1800, and PCS 1900 applications. Its fast transient
response also makes the Si4114G especially well suited
to GPRS multislot applications where channel switching
and settling times are critical. This IC, with a minimum
number of external components, is all that is necessary
to implement the frequency synthesis function.
The Si4114G has two complete phase-locked loops
(PLLs) with integrated voltage-controlled oscillators
(VCOs). The low phase noise of the VCOs makes the
Si4114G suitable for use in demanding wireless
communications applications. Also integrated are phase
detectors, loop filters, and reference dividers. The IC is
programmed through a three-wire serial interface.
Two RF PLLs are provided to cover the 1710–
1990 MHz frequency span. RF1 covers 1840–
1990 MHz; RF2 covers 1710–1840 MHz.
The center frequency of each VCO is set by an internal
L-C tank circuit. Inaccuracies in this tank due to
temperature or small manufacturing offsets are
compensated for by the Si4114G’s proprietary self-
tuning algorithm. This algorithm is initiated each time
the PLL is powered up (by either the PWDN
pin or by
software) and/or each time a new output frequency is
programmed.
The unique PLL architecture used in the Si4114G
produces a transient response that is superior in speed
to fractional-N architectures without suffering the high
phase noise or spurious modulation effects often
associated with those designs.
3.1. Serial Interface
A timing diagram for the serial interface is shown in
Figure 2 on page 7. Figure 3 on page 7 shows the
format of the serial word.
The Si4114G is programmed serially with 22-bit words
comprised of 18-bit data fields and 4-bit address fields.
When the serial interface is enabled (i.e., when SEN
is
low) data and address bits on the SDATA pin are
clocked into an internal shift register on the rising edge
of SCLK. Data in the shift register is then transferred on
the rising edge of SEN
into the internal data register
addressed in the address field. The serial interface is
disabled when SEN
is high.
Table 7 on page 17 summarizes the data register
functions and addresses. The internal shift register will
ignore any leading bits before the 22 required bits.
3.2. Self-Tuning Algorithm
The self-tuning algorithm is initiated immediately
following powerup of a PLL or, if the PLL is already
powered, following a change in its programmed output
frequency. This algorithm attempts to coarse-tune the
VCO so that its free-running frequency is near the
desired output frequency. In so doing, the algorithm will
compensate for errors in the L-C tank circuit. It will also
reduce the frequency error for which the PLL must
correct to get the precise desired output frequency. The
self-tuning algorithm will leave the VCO oscillating at a
frequency in error by somewhat less than 1% of the
desired output frequency.
After self-tuning, the PLL controls the VCO oscillation
frequency. The PLL will complete frequency locking,
eliminating any remaining frequency error. Thereafter, it
will maintain frequency lock, compensating for effects
caused by temperature and supply voltage variations.
The Si4114G’s self-tuning algorithm will compensate for
component value errors at any temperature within the
specified temperature range. However, the ability of the
PLL to compensate for drift in component values that
occur AFTER self-tuning is limited. The PLL will be able
to maintain lock for changes in temperature of
approximately ±30 °C.
Applications such as GSM handsets where the PLL is
regularly powered down or switched between channels
eliminate the potential effects of temperature drift
because the VCO is re-tuned when it is powered up or
when a new frequency is programmed. In applications
where the ambient temperature can drift substantially
after self-tuning, it may be necessary to monitor the
LDETB (lock-detect bar) signal on the AUXOUT pin to
determine the locking state of the PLL. (See "3.8.
Auxiliary Output (AUXOUT)" on page 15 for how to
select LDETB.)
The LDETB signal is normally low after self-tuning is
completed but will rise when the PLL nears the limit of
its compensation range (LDETB will also be high when
either PLL is executing the self-tuning algorithm). The
output frequency will still be locked when LDETB goes
high, but the PLL will eventually lose lock if the
temperature continues to drift in the same direction.
Therefore, if LDETB goes high the RF PLLs should
promptly be re-tuned by initiating the self-tuning
algorithm.
3.3. Output Frequencies
The RF output frequencies are set by programming the
N-Divider registers. Each RF PLL has its own N register
and can be programmed independently. Programming
the N-Divider register for either RF1 or RF2
