Si4114G
Rev. 1.1 7
Figure 2. Serial Interface Timing Diagram
Figure 3. Serial Word Format
D17 D16 D15 A1 A0
t
su
t
en1
t
hold
t
w
t
en2
t
en3
SCLK
SDATA
SENB
D
17
D
16
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
3
A
2
A
1
A
0
data
field
address
field
First bit
clocked in
Last bit
clocked in
Si4114G
8 Rev. 1.1
Table 5. RF Synthesizer Characteristics
(V
DD
= 2.7 to 2.9 V, T
A
= –20 to 70 °C)
Parameter
1
Symbol Test Condition Min Typ Max Unit
XIN Input Frequency f
REF
13 26 MHz
Reference Amplifier Sensitivity V
REF
0.5 V
DD
+0.3
V
PP
Phase Detector Update Frequency f
φ
f
φ
= f
REF
/R 200 KHz
RF1 Tuning Range
1840 1990 MHz
RF2 Tuning Range 1710 1840 MHz
RF1 VCO Pushing Open loop 500 kHz/V
RF2 VCO Pushing 400 kHz/V
RF1 VCO Pulling VSWR = 2:1, all
phases, open loop
400 kHz
PP
RF2 VCO Pulling 100 kHz
PP
RF1 Phase Noise
2
1 MHz offset –132 –130.5 dBc/Hz
1.6 MHz offset –137 –135.5 dBc/Hz
3 MHz offset –142 –140.5 dBc/Hz
RF1 Integrated Phase Error 100 Hz to 100 kHz 1.0 deg rms
RF2 Phase Noise
2
1 MHz offset –134 –132 dBc/Hz
1.6 MHz offset –139 –137 dBc/Hz
3 MHz offset –144 –142 dBc/Hz
RF2 Integrated Phase Error 100 Hz to 100 kHz 0.8 deg rms
RF1 Harmonic Suppression Second Harmonic –26 dBc
RF2 Harmonic Suppression –26 dBc
RFOUT Power Level
3
RF1 active, Z
L
= 50 –6 –2.4 0 dBm
RFOUT Power Level
3
RF2 active, Z
L
= 50 –6.5 –4 0 dBm
RF1 Reference Spurs
2
Offset = 200 kHz –70 –63 dBc
Offset = 400 kHz –75 –67 dBc
Offset = 600 kHz –80 –70 dBc
RF2 Reference Spurs
2
Offset = 200 kHz –67 –63 dBc
Offset = 400 kHz –71 –67 dBc
Offset = 600 kHz –75 –70 dBc
Powerup Request to Synthesizer Ready
Time, RF1, RF2
4
t
pup
Figures 4, 5 140 µs
Powerdown Request to Synthesizer Off
Time
5
t
pdn
Figures 4, 5 100 ns
Notes:
1.
RF1 = 1.92 GHz, RF2 = 1.78 GHz for all parameters unless otherwise noted.
2. Maximum values guaranteed by design.
3. RF1 = 1.90 GHz, RF2 = 1.80 GHz, T
A
= –10 to +55 °C.
4. From powerup request (PWDN or SEN during a write of 1 to bit PDRB in Register 2) to RF synthesizers ready
(settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is 120
µs.
5. From powerdown request (PWDN, or SENduring a write of 0 to bit PDRB in Register 2) to supply current equal to
I
PWDN
.
Si4114G
Rev. 1.1 9
Figure 4. Software Power Management Timing Diagram
Figure 5. Hardware Power Management Timing Diagram
PDRB = 0PDRB = 1
t
pup
t
pdn
I
T
I
PWDN
SEN
SDATA
RF synthesizers settled to within
0.1 ppm frequency error.
t
pup
t
pdn
I
T
I
PWDN
PWDN
RF synthesizers settled to within
0.1 ppm frequency error.

SI4114G-B-GM

Mfr. #:
Manufacturer:
Silicon Labs
Description:
RF Wireless Misc GSM Frequency Synthesizer for Direct Conversion, lead free Not recommended for new designs, Recommended replacement is multiple Si41xx-D-GM devices
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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