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SI4114G-B-GM

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
Si4114G
4 Rev. 1.1
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Temperature T
A
–20 25 70 °C
Supply Voltage V
DD
2.7 2.8 2.9 V
Supply Voltages Difference V
∆
(V
DDR
– V
DDD
),
(V
DDI
– V
DDD
)
–0.3 — 0.3 V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at 3.0 V and an operating temperature of 25°C unless otherwise stated.
Table 2. Absolute Maximum Ratings
1,2
Parameter Symbol Value Unit
DC Supply Voltage V
DD
–0.5 to 4.0 V
Input Current
3
I
IN
±10 mA
Input Voltage
3
V
IN
–0.3 to V
DD
+0.3 V
Storage Temperature Range T
STG
–55 to 150 °C
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. This device is a high performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of
this device should only be done at ESD-protected workstations.
3. For signals SCLK, SDATA, SEN
, PWDN, and XIN.
Si4114G
Rev. 1.1 5
Table 3. DC Characteristics
(V
DD
= 2.7 to 2.9 V, T
A
= –20 to 70 °C
Parameter Symbol Test Condition Min Typ Max Unit
RF1 Mode Supply Current
1
RF1 active — 14 18 mA
RF2 Mode Supply Current
1
RF2 active — 13 18 mA
Standby Current PWDN
= 0 — 1 — µA
High Level Input Voltage
2
V
IH
0.7 V
DD
——V
Low Level Input Voltage
2
V
IL
— — 0.3 V
DD
V
High Level Input Current
2
I
IH
V
IH
= 3.6 V,
V
DD
= 3.6 V
–10 — 10 µA
Low Level Input Current
2
I
IL
V
IL
= 0 V,
V
DD
= 3.6 V
–10 — 10 µA
High Level Output Voltage
3
V
OH
I
OH
= –500 µA V
DD
–0.4 — — V
Low Level Output Voltage
3
V
OL
I
OH
= 500 µA — — 0.4 V
Notes:
1. RF1 = 1.92 GHz, RF2 = 1.78 GHz
2. For signals SCLK, SDATA, SEN
, and PWDN.
3. For signal AUXOUT.
Si4114G
6 Rev. 1.1
Figure 1. SCLK Timing Diagram
Table 4. Serial Interface Timing
(V
DD
= 2.7 to 2.9 V, T
A
= –20 to 70 °C)
Parameter
1
Symbol Test Condition Min Typ Max Unit
SCLK Cycle Time t
clk
Figure 1 40 — — ns
SCLK Rise Time t
r
Figure 1 — — 50 ns
SCLK Fall Time t
f
Figure 1 — — 50 ns
SCLK High Time t
h
Figure 1 10 — — ns
SCLK Low Time t
l
Figure 1 10 — — ns
SDATA Setup Time to SCLK↑
2
t
su
Figure 2 5 — — ns
SDATA Hold Time from SCLK↑
2
t
hold
Figure 2 0 — — ns
SEN
↓ to SCLK↑ Delay Time
2
t
en1
Figure 2 10 — — ns
SCLK↑ to SEN
↑ Delay Time
2
t
en2
Figure 2 12 — — ns
SEN
↑ to SCLK↑ Delay Time
2
t
en3
Figure 2 12 — — ns
SEN
Pulse Width t
w
Figure 2 10 — — ns
Notes:
1. All timing is referenced to the 50% level of the waveform, unless otherwise noted.
2. Timing is not referenced to 50% level of waveform. See Figure 2.
SCLK
80%
20%
50%
t
r
t
f
t
l
t
clk
t
h
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

SI4114G-B-GM

Mfr. #:
Buy SI4114G-B-GM
Manufacturer:
Silicon Labs
Description:
RF Wireless Misc GSM Frequency Synthesizer for Direct Conversion, lead free Not recommended for new designs, Recommended replacement is multiple Si41xx-D-GM devices
Lifecycle:
New from this manufacturer.
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