15
COMMERCIAL TEMPERATURE RANGE
IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at least two flip-flop stages.
This is done to improve flag signal reliability by reducing the probability of
metastable events when CLKA operates asynchronously with respect to either
CLKB or CLKC. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to
CLKA. EFB/ORB and AEB are synchronized to CLKB. FFC/IRC and AFC are
synchronized to CLKC. Tables 5 and 6 show the relationship of each port flag
to FIFO1 and FIFO2.
EMPTY/OUTPUT READY FLAGS (EFA/ORA, EFB/ORB)
These are dual purpose flags. In the FWFT mode, the Output Ready (ORA,
ORB) function is selected. When the Output Ready flag is HIGH, new data is
present in the FIFO output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
In the IDT Standard mode, the Empty Flag (EFA, EFB) function is selected.
When the Empty Flag is HIGH, data is available in the FIFO’s RAM memory for
reading to the output register. When the Empty Flag is LOW, the previous data
word is present in the FIFO output register and attempted FIFO reads are
ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock that
reads data from its array. For both the FWFT and IDT Standard modes, the FIFO
read pointer is incremented each time a new word is clocked to its output register.
The state machine that controls an Output Ready flag monitors a write pointer
and read pointer comparator that indicates when the FIFO memory status is
empty, empty+1, or empty+2.
In FWFT mode, from the time a word is written to a FIFO, it can be shifted to
the FIFO output register in a minimum of three cycles of the Output Ready flag
synchronizing clock. Therefore, an Output Ready flag is LOW if a word in
memory is the next data to be sent to the FlFO output register and three cycles
of the port clock that reads data from the FIFO have not elapsed since the time
the word was written. The Output Ready flag of the FIFO remains LOW until the
third LOW-to-HIGH transition of the synchronizing clock occurs, simultaneously
forcing the Output Ready flag HIGH and shifting the word to the FIFO output
register.
In IDT Standard mode, from the time a word is written to a FIFO, the Empty
Flag will indicate the presence of data available for reading in a minimum of two
cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW
if a word in memory is the next data to be sent to the FlFO output register and
two cycles of the port Clock that reads data from the FIFO have not elapsed since
the time the word was written. The Empty Flag of the FIFO remains LOW until
the second LOW-to-HIGH transition of the synchronizing clock
occurs, forcing
the Empty Flag HIGH; only then can data be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing
clock begins the first synchronization cycle of a write if the clock transition occurs
at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle
can be
the first synchronization cycle (see Figure 16, 17, 18 and 19).
FULL/INPUT READY FLAGS (FFA/IRA, FFC/IRC)
These are dual purpose flags. In FWFT mode, the Input Ready (IRA and
IRC) function is selected. In IDT Standard mode, the Full Flag (FFA and FFC)
function is selected. For both timing modes, when the Full/Input Ready flag is
HIGH, a memory location is free in the FIFO to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
The Full/Input Ready flag of a FlFO is synchronized to the port clock that writes
data to its array. For both FWFT and IDT Standard modes, each time a word
is written to a FIFO, its write pointer is incremented. The state machine that
controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory location is ready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than two
cycles of the Full/Input Ready flag synchronizing clock have elapsed since the
next memory write location has been read. The second LOW-to-HIGH transition
on the Full/Input Ready flag synchronizing clock after the read sets the Full/Input
Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
begins the first synchronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figure 20, 21, 22, and 23).
ALMOST-EMPTY FLAGS (AEA, AEB)
The Almost-Empty flag of a FIFO is synchronized to the port clock that reads
data from its array. The state machine that controls an Almost-Empty flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-empty state is defined by the contents of register X1 for AEB and register
X2 for AEA. These registers are loaded with preset values during a FIFO reset,
programmed from Port A, or programmed serially (see the Almost-Empty flag
and Almost-Full flag offset programming section). An Almost-Empty flag is LOW
when its FIFO contains X or less words and is HIGH when its FIFO contains
(X+1) or more words. A data word present in the FIFO output register has been
read from memory.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clock
are required after a FIFO write for its Almost-Empty flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of its synchronizing clock have not elapsed since the
write that filled the memory to the (X+1) level. An Almost-Empty flag is set HIGH
by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO
write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an Almost-
Empty flag synchronizing clock begins the first synchronization cycle if it occurs
at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be the first synchro-
nization cycle. (See Figure 24 and 25).
ALMOST-FULL FLAGS (AFA, AFC)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors a
write pointer and read pointer comparator that indicates when the FIFO memory
status is almost-full, almost-full-1, or almost-full-2. The almost-full state is defined
by the contents of register Y1 for AFA and register Y2 for AFC. These registers
are loaded with preset values during a FlFO reset, programmed from Port A,
or programmed serially (see Almost-Empty flag and Almost-Full flag offset
programming section). An Almost-Full flag is LOW when the number of words
in its FIFO is greater than or equal to (16,384-Y), (32,768-Y), or (65,536-Y)
for the IDT72V3686, IDT72V3696, or IDT72V36106 respectively. An Almost-
Full flag is HIGH when the number of words in its FIFO is less than or equal to
[16,384-(Y+1)], [32,768-(Y+1)], or [65,536-(Y+1)] for the IDT72V3686,
IDT72V3696, or IDT72V36106 respectively. Note that a data word present in
the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are
required after a FIFO read for its Almost-Full flag to reflect the new level of fill.
Therefore, the Almost-Full flag of a FIFO containing [16,384/32,768/65,536-
(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have
not elapsed since the read that reduced the number of words in memory to
