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IDT72V36106L15PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
7
COMMERCIAL TEMPERATURE RANGE
IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
Symbol Rating Commercial Unit
VCC Supply Voltage Range –0.5 to +4.6 V
VI
(2)
Input Voltage Range –0.5 to VCC+0.5 V
VO
(2)
Output Voltage Range –0.5 to VCC+0.5 V
IIK Input Clamp Current (VI < 0 or VI > VCC) ±20 mA
IOK Output Clamp Current (VO = < 0 or VO > VCC) ±50 mA
I
OUT Continuous Output Current (VO = 0 to VCC) ±50 mA
I
CC Continuous Current Through VCC or GND ±400 mA
TSTG Storage Temperature Range –65 to 150 °C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)
(1)
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25°C.
2. Vcc = 3.3V ± 0.15V, TA = 0° to +70°; JEDEC JESD8-A compliant.
3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
4. Characterized values, not currently tested.
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
RECOMMENDED OPERATING CONDITIONS
NOTE:
1. Vcc = 3.3V ± 0.15V, JEDEC JESD8-A compliant
Symbol Parameter Min. Typ. Max. Unit
V
CC Supply Voltage 3.15 3.3 3.45 V
VIH High-Level Input Voltage 2 — VCC+0.5 V
V
IL Low-Level Input Voltage — — 0.8 V
I
OH High-Level Output Current — — –4 mA
IOL Low-Level Output Current — — 8 mA
T
A Operating Temperature 0 — 70 °C
IDT72V3686
IDT72V3696
IDT72V36106
Commercial
tCLK = 10, 15 ns
(2)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VOH Output Logic "1" Voltage VCC = 3.0V, IOH = –4 mA 2.4 — — V
VOL Output Logic "0" Voltage VCC = 3.0V, IOL = 8 mA — — 0.5 V
I
LI Input Leakage Current (Any Input) VCC = 3.6V, VI = VCC or 0 — — ±5 µA
ILO Output Leakage Current VCC = 3.6V, VO = VCC or 0 — — ±5 µA
ICC2
(3)
Standby Current (with CLKA, CLKB and CLKC running) VCC = 3.6V, VI = VCC - 0.2V or 0 — — 15 mA
I
CC3
(3)
Standby Current (no clocks running) VCC = 3.6V, VI = VCC - 0.2V or 0 — — 5 mA
CIN
(4)
Input Capacitance VI = 0, f = 1 MHz — 4 — pF
COUT
(4)
Output Capacitance VO = 0, f = 1 MHZ — 8 — pF
8
COMMERCIAL TEMPERATURE RANGE
IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3686/72V3696/72V36106 with CLKA,
CLKB and CLKC set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs
driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With I
CC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x ICC(f) + Σ(CL x VCC
2
x fo)
N
where:
N = number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)
CL = output capacitance load
fo = switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
010203040506070
0
10
20
30
40
50
60
f
S
⎯ Clock Frequency ⎯ MHz
I
CC(f)
Supply Current
mA
f
data
= 1/2
f
S
T
A
= 25°C
C
L
= 0 pF
4676 drw03
70
90
80
100
80
90
100
V
CC =
3.3V
V
CC =
3.6V
V
CC =
3.0V
9
COMMERCIAL TEMPERATURE RANGE
IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
IDT72V3686L10 IDT72V3686L15
IDT72V3696L10 IDT72V3696L15
IDT72V36106L10 IDT72V36106L15
Symbol Parameter Min. Max. Min. Max. Unit
fS Clock Frequency, CLKA, CLKB, or CLKC — 100 — 66.7 MHz
tCLK Clock Cycle Time, CLKA, CLKB, or CLKC 10 — 15 — ns
tCLKH Pulse Duration, CLKA, CLKB, or CLKC HIGH 4.5 — 6 — ns
tCLKL Pulse Duration, CLKA, CLKB, OR CLKC LOW 4.5 — 6 — ns
tDS Setup Time, A0-A35 before CLKA↑ and C0-C17 before CLKC↑ 3—4—ns
tENS1 Setup Time, CSA and W/RA before CLKA↑; CSB 4 — 4.5 — ns
before CLKB↑
tENS2 Setup Time, ENA, and MBA before CLKA↑; RENB 3 — 4.5 — ns
and MBB before CLKB↑; WENC and MBC before CLKC↑
tRSTS Setup Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 5—5—ns
LOW before CLKA↑ or CLKB↑
(1)
tFSS Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH 7.5 — 8.5 — ns
tBES Setup Time, BE/FWFT before MRS1 and MRS2 HIGH 7.5 — 7.5 — ns
tSDS Setup Time, FS0/SD before CLKA↑ 3—4—ns
tSENS Setup Time, FS1/SEN before CLKA↑ 3—4—ns
tFWS Setup Time, BE/FWFT before CLKA↑ 0—0—ns
tRTMS Setup Time, RTM before RT1; RTM before RT2 5—5—ns
tDH Hold Time, A0-A35 after CLKA↑ and C0-C17 after CLKC↑ 0.5 — 1 — ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, 0.5 — 1 — ns
RENB, and MBB after CLKB↑; WENC and MBC after CLKC↑
tRSTH Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 4—4—ns
LOW after CLKA↑ or CLKB↑
(1)
tFSH Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH 2 — 2 — ns
tBEH Hold Time, BE/FWFT after MRS1 and MRS2 HIGH 2 — 2 — ns
tSDH Hold Time, FS0/SD after CLKA↑ 0.5 — 1 — ns
tSENH Hold Time, FS1/SEN HIGH after CLKA↑ 0.5 — 1 — ns
tSPH Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH 2 — 2 — ns
tRTMH Hold Time, RTM after RT1; RTM after RT2 5—5—ns
tSKEW1
(2)
Skew Time, between CLKA↑ and CLKB↑ for EFB/ORB and 5 — 7.5 — ns
FFA/IRA; between CLKA↑ and CLKC↑ for EFA/ORA and
FFC/IRC
tSKEW2
(2,3)
Skew Time, between CLKA↑ and CLKB↑ for AEB and AFA;12—12—ns
between CLKA↑ and CLKC↑ for AEA and AFC
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.
3. Design simulated, not tested.
(Vcc = 3.3V ± 0.15V; TA = 0
ο
C to +70
ο
C; JEDEC JESD8-A compliant)
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IDT72V36106L15PF8

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Description:
IC FIFO 131KX36 15NS 128QFP
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