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IDT72V36106L15PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
34
COMMERCIAL TEMPERATURE RANGE
IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
Figure 28. Timing for Mail1 Register and
MBF1MBF1
MBF1MBF1
MBF1
Flag (IDT Standard and FWFT Modes)
Figure 29. Timing for Mail2 Register and
MBF2MBF2
MBF2MBF2
MBF2
Flag (IDT Standard and FWFT Modes)
4676 drw 30
CLKA
ENA
A0-A35
MBA
CSA
W/RA
CLKB
MBF1
CSB
MBB
RENB
B0-B17
W1
t
ENS1
t
ENH
t
DS
t
DH
t
PMF
t
PMF
t
ENS2
t
ENH
t
DIS
t
EN
t
MDV
t
PMR
FIFO1 Output Register
W1 (Remains valid in Mail1 Register after read)
t
ENS1
t
ENH
t
ENS2
t
ENH
t
ENS2
t
ENH
4676 drw 31
CLKC
ENC
C0-C17
MBC
CLKA
MBF2
CSA
MBA
ENA
A0-A35
W/RA
W1
t
DS
t
DH
t
PMF
t
PMF
t
ENS2
t
ENH
t
DIS
t
EN
t
MDV
t
PMR
FIFO2 Output Register
W1 (Remains valid in Mail2 Register after read)
t
ENS2
t
ENH
t
ENS2
t
ENH
NOTE:
1. If Port C is configured for word size, data can be written to the Mail2 register using C0-C17. In this first case, A18-A35 will have valid data (A0-A17 will be indeterminate). If Port C is configured
for byte size, data can be written to the Mail2 register using C0-C8 (C9-C17 are don't care inputs). In this second case, A18-A26 will have valid data (A0-A17 and A27-A35 will be
indeterminate).
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data. If Port
B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B17 will
be indeterminate).
35
COMMERCIAL TEMPERATURE RANGE
IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
CLKA
RENB
CLKB
RT1
4676 drw 32
t
RSTS
t
RSTH
t
REF
(2)
B0-Bn
RTM
EFB
t
REF
(2)
W1
Wx
t
A
t
ENS2
t
ENH
13
4
2
1
342
t
RTMS
t
RTMH
NOTES:
1. CSB = LOW
2. Retransmit setup is complete after EFB returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, FFA will be LOW throughout the Retransmit
setup procedure. D = 16,384, 32,768 and 65,536 for the IDT72V3686, IDT72V3696 and IDT72V36106 respectively.
Figure 30. Retransmit Timing for FIFO1 (IDT Standard Mode)
NOTES:
1. CSA = LOW
2. Retransmit setup is complete after EFA returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO2.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, FFC will be LOW throughout the Retransmit
setup procedure. D = 16,384, 32,768 and 65,536 for the IDT72V3686, IDT72V3696 and IDT72V36106 respectively.
Figure 31. Retransmit Timing for FIFO2 (IDT Standard Mode)
CLKC
ENA
CLKA
RT2
4676 drw 33
t
RSTS
t
RSTH
t
REF
(2)
A0-An
RTM
EFA
t
REF
(2)
W1
Wx
t
A
t
ENS2
t
ENH
13
4
2
1
342
t
RTMS
t
RTMH
36
COMMERCIAL TEMPERATURE RANGE
IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
CLKA
RENB
CLKB
RT1
4676 drw 34
t
RSTS
t
RSTH
t
REF
(2)
B0-Bn
RTM
ORB
t
REF
(2)
W1
Wx
t
A
13
4
2
1
342
t
RTMS
t
RTMH
LOW
NOTES:
1. CSB = LOW
2. Retransmit setup is complete after ORB returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, IRA will be LOW throughout the Retransmit
setup procedure. D = 16,385, 32,769 and 65,537 for the IDT72V3686, IDT72V3696 and IDT72V36106 respectively.
Figure 32. Retransmit Timing for FIFO1 (FWFT Mode)
CLKC
ENA
CLKA
RT2
4676 drw 35
t
RSTS
t
RSTH
t
REF
(2)
A0-An
RTM
ORA
t
REF
(2)
W1
Wx
t
A
13
4
2
1
342
t
RTMS
t
RTMH
LOW
NOTES:
1. CSA = LOW
2. Retransmit setup is complete after ORA returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO2 after Master Reset on FIFO2.
4. No more than D-2 may be written to the FIFO2 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, IRC will be LOW throughout the Retransmit
setup procedure. D = 16,385, 32,769 and 65,537 for the IDT72V3686, IDT72V3696 and IDT72V36106 respectively.
Figure 33. Retransmit Timing for FIFO2 (FWFT Mode)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

IDT72V36106L15PF8

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Description:
IC FIFO 131KX36 15NS 128QFP
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