27
COMMERCIAL TEMPERATURE RANGE
IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the CLKC edge and the rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
2. If Port C size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte write of the long word, respectively.
Figure 18. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)
MBC
C0-C17
CLKA
CSA
W/RA
MBA
WENC
ENA
A0-A35
CLKC
12
4676 drw 20
tCLKH
tCLKL
tCLK
tENS2
tENS2
tENH
tENH
tDS tDH
tSKEW1
tCLK
tCLKL
tENS2
tENH
tA
W1
FIFO2 Empty
LOW
LOW
LOW
tCLKH
HIGH
(1)
tREF
tDH
tDS
Write 1
Write 2
ORA
IRC
3
Old Data in FIFO2 Output Register
tREF
