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IDT72V36106L15PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
4
COMMERCIAL TEMPERATURE RANGE
IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
PIN DESCRIPTIONS
Symbol Name I/O Description
A0-A35 Port A Data I/O 36-bit bidirectional data port for side A.
AEA Port A Almost- O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2
Empty Flag is less than or equal to the value in the Almost-Empty A Offset register, X2.
AEB Port B Almost- O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1
Empty Flag is less than or equal to the value in the Almost-Empty B Offset register, X1.
AFA Port A Almost- O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations
Full Flag in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
AFC Port C Almost- O Programmable Almost-Full flag synchronized to CLKC. It is LOW when the number of empty locations
Full Flag in FIFO2 is less than or equal to the value in the Almost-Full C Offset register, Y2.
B0-B17 Port B Data O 18-bit output data port for side B.
BE/FWFT Big-Endian/ I This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation.
First Word Fall In this case, depending on the bus size, the most significant byte or word on Port A is read from
Through Select Port B first (A-to-B data flow) or is written to Port C first (C-to-A data flow). A LOW on BE will select
Little-Endian operation. In this case, the least significant byte or word on Port A is read from Port B first
(A-to-B data flow) or is written to Port C first (C-to-A data flow).
After Master Reset, this pin selects the timing mode. A HIGH on FWFT selects IDT Standard mode, a
LOW selects First Word Fall Through mode. Once the timing mode has been selected, the level on
FWFT must be static throughout device operation.
C0-C17 Port C Data I 18-bit input data port for side C.
CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through Port A and can be
asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to
the LOW-to-HIGH transition of CLKA.
CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous
or coincident to CLKA. EFB/ORB and AEB are synchronized to the LOW-to-HIGH transition of CLKB.
CLKC Port C Clock I CLKC is a continuous clock that synchronizes all data transfers through Port C and can be asynchronous
or coincident to CLKA. FFC/IRC and AFC are synchronized to the LOW-to-HIGH transition of CLKC.
CSA Port A Chip I CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35
Select outputs are in the high-impedance state when CSA is HIGH.
CSB Port B Chip I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read data on Port B. The B0-B17
Select outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA Port A Empty/ O This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates
Output Ready whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA
Flag indicates the presence of valid data on the A0-A35 outputs, available for reading. EFA/ORA is
synchronized to the LOW-to-HIGH transition of CLKA.
EFB/ORB Port B Empty/ O This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates
Output Ready Flag whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB
indicates the presence of valid data on the B0-B17 outputs, available for reading. EFB/ORB is synchronized
to the LOW-to-HIGH transition of CLKB.
ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
FFA/IRA Port A Full/ O This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates
Input Ready Flag whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA
indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is
synchronized to the LOW-to-HIGH transition of CLKA.
FFC/IRC Port C Full/ O This is a dual function pin. In the IDT Standard mode, the FFC function is selected. FFC indicates
Input Ready Flag whether or not the FIFO2 memory is full. In the FWFT mode, the IRC function is selected. IRC
indicates whether or not there is space available for writing to the FIFO2 memory. FFC/IRC is
synchronized to the LOW-to-HIGH transition of CLKC.
5
COMMERCIAL TEMPERATURE RANGE
IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
PIN DESCRIPTIONS (CONTINUED)
Symbol Name I/O Description
FS0/SD Flag Offset Select 0/ I FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During Master Reset,
Serial Data FS1/SEN and FS0/SD, together with FS2, select the flag offset programming method. Three Offset register
programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or 1,024),
FS1/SEN Flag Offset Select 1/ I parallel load from Port A, and serial load.
Serial Enable
When serial load is selected for flag Offset register programming, FS1/SEN is used as an enable synchronous to
FS2
(1)
Flag Offset Select 2 I the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on
FS0/SD into the X and Y registers. The number of bit writes required to program the Offset registers is 56 for the
72V3686, 60 for the 72V3696, and 64 for the 72V36106. The first bit write stores the Y-register (Y1) MSB and
the last bit write stores the X-register (X2) LSB.
LOOP Loopback Select I This pin selects the loopback feature for Port A. During Loopback data from FIFO2 will be directed to the input of
FIFO1. to initiate a Loop the LOOP pin must be held LOW and the ENA pin must be HIGH.
MBA Port A Mailbox I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
Select outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects
FIFO2 output-register data for output.
MBB Port B Mailbox I A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are
Select active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1 output
register data for output.
MBC Port C Mailbox I A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during
Select Master Reset.
MBF1 Mail1 Register O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1
Flag register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2 Mail2 Register O MBF2 is set LOW by a LOW-to-HIGH transition of CLKC that writes data to the mail2 register. Writes to the mail2
Flag register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a
Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1 Master Reset I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming method (serial or
parallel) and one of five programmable flag default offsets for FIFO1 and FIFO2. It also configures ports B and
C for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH
transitions of CLKB must occur while MRS1 is LOW.
MRS2 Master Reset I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
output register to all zeroes. A LOW-to-HIGH transition on MRS2, toggled simultaneously with MRS1, selects
the programming method (serial or parallel) and one of the five flag default offsets for FIFO2. Four LOW-to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKC must occur while MRS2 is LOW.
PRS1/ Partial Reset/ I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin. If RTM
RT1 Retransmit FIFO1 is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes the FIFO1 read and write
pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset, the currently
selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are
all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO1 read pointer only to
the first memory location.
PRS2/ Partial Reset/ I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin. If RTM
RT2 Retransmit FIFO2 is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes the FIFO2 read and write
selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are
all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO2 read pointer only to
the first memory location.
RENB Port B Read Enable I RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on Port B.
RTM Retransmit Mode I This pin is used in conjunction with the RT1 and RT2 pins. When RTM is HIGH a Retransmit is performed on FIFO1
or FIFO2 respectively.
6
COMMERCIAL TEMPERATURE RANGE
IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
SIZEB
(1)
Port B I SIZEB determines the bus width of Port B. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
Bus Size Select selects word (18-bit) bus size. SIZEB works with SIZEC and BE to select the bus size and endian arrangement
for ports B and C. The level of SIZEB must be static throughout device operation.
SIZEC
(1)
Port C I SIZEC determines the bus width of Port C. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
Bus Size Select selects word (18-bit) bus size. SIZEC works with SIZEB and BE to select the bus size and endian arrangement
for ports B and C. The level of SIZEC must be static throughout device operation.
WENC Port C Write Enable I WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on Port C.
W/RA Port A Write/ I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of
Read Select CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
PIN DESCRIPTIONS (CONTINUED)
Symbol Name I/O Description
NOTE:
1. FS2, SIZEB and SIZEC inputs are not TTL compatible. These inputs should be tied to GND or V
CC.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

IDT72V36106L15PF8

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IC FIFO 131KX36 15NS 128QFP
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