R8C/33T Group 2. Central Processing Unit (CPU)
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2.1 Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-
bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5 Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5 Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
R8C/33T Group 2. Central Processing Unit (CPU)
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2.8.7 Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
R8C/33T Group 3. Memory
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3. Memory
3.1 R8C/33T Group
Figure 3.1 is a Memory Map of R8C/33T Group. The R8C/33T Group has a 1-Mbyte address space from addresses
00000h to FFFFFh. For example, a 32-Kbyte internal ROM area is allocated addresses 08000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal
RAM area is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral
function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be
accessed by users.
Figure 3.1 Memory Map of R8C/33T Group
0FFFFh
0FFDCh
Notes:
1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).
2. The blank areas are reserved and cannot be accessed by users.
FFFFFh
0FFFFh
0YYYYh
0XXXXh
00400h
002FFh
00000h
Internal ROM
(program ROM)
Internal RAM
SFR
(Refer to 4. Special Function
Registers (SFRs))
02FFFh
02C00h
SFR
(Refer to 4. Special Function
Registers (SFRs))
ZZZZZh
Internal ROM
(program ROM)
03FFFh
03000h
Internal ROM
(data flash)
(1)
0FFD8h
Reserved area
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer, oscillation stop detection, voltage monitor
Address break
(Reserved)
Reset
Part Number
R5F21334TNFP, R5F21334TDFP,
R5F21334TNXXXFP, R5F21334TDXXXFP
R5F21335TNFP, R5F21335TDFP,
R5F21335TNXXXFP, R5F21335TDXXXFP
R5F21336TNFP, R5F21336TDFP,
R5F21336TNXXXFP, R5F21336TDXXXFP
Size Address 0YYYYh
16 Kbytes
24 Kbytes
32 Kbytes
0C000h
0A000h
08000h
Internal ROM
Address ZZZZZh
Address 0XXXXhSize
1.5 Kbytes
2 Kbytes
2.5 Kbytes
009FFh
00BFFh
00DFFh
Internal RAM

R5F21336TNFP#50

Mfr. #:
Manufacturer:
Renesas Electronics
Description:
16-bit Microcontrollers - MCU R8/C33T 32+4K 1.8/5.5V -20TO85 32LQFP TR
Lifecycle:
New from this manufacturer.
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