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R5F21336TNFP#50

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
R8C/33T Group 5. Electrical Characteristics
R01DS0046EJ0110 Rev.1.10 Page 31 of 47
Apr 26, 2011
Notes:
1. Vcc = 2.7 V to 5.5 V at Topr =
−20°C to 85°C (N version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Figure 5.2 Time delay until Suspend
Table 5.5 Flash Memory (Data flash Block A to Block D) Electrical Characteristics
Symbol Parameter Conditions
Standard
Unit
Min. Typ. Max.
—
Program/erase endurance
(2)
10,000
(3)
——times
— Byte program time
(program/erase endurance
≤ 1,000 times)
— 160 1,500
µs
— Byte program time
(program/erase endurance
> 1,000 times)
— 300 1,500
µs
— Block erase time
(program/erase endurance
≤ 1,000 times)
—0.2 1 s
— Block erase time
(program/erase endurance
> 1,000 times)
—0.3 1 s
t
d(SR-SUS) Time delay from suspend request until
suspend
— — 5 + CPU clock
× 3 cycles
ms
— Interval from erase start/restart until
following suspend request
0— —
µs
— Time from suspend until erase restart — — 30 + CPU clock
× 1 cycle
µs
t
d(CMDRST
-READY)
Time from when command is forcibly
terminated until reading is enabled
— — 30 + CPU clock
× 1 cycle
µs
— Program, erase voltage 2.7 — 5.5 V
— Read voltage 1.8 — 5.5 V
— Program, erase temperature
−20
—85
°C
—
Data hold time
(7)
Ambient temperature = 55°C 20 — — year
FST6 bit
Suspend request
(FMR21 bit)
FST6, FST7: Bit in FST register
FMR21: Bit in FMR2 register
FST7 bit
Fixed time
td(SR-SUS)
Clock-dependent time
Access restart
R8C/33T Group 5. Electrical Characteristics
R01DS0046EJ0110 Rev.1.10 Page 32 of 47
Apr 26, 2011
Notes:
1. The measurement condition is Vcc = 1.8 V to 5.5 V and Topr =
−20°C to 85°C (N version).
2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
4. Time until the voltage monitor 0 reset is generated after the voltage passes V
det0.
Notes:
1. The measurement condition is Vcc = 1.8 V to 5.5 V and Topr =
−20°C to 85°C (N version).
2. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
3. Time until the voltage monitor 1 interrupt request is generated after the voltage passes V
det1.
4. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
Table 5.6 Voltage Detection 0 Circuit Electrical Characteristics
Symbol Parameter Condition
Standard
Unit
Min. Typ. Max.
V
det0
Voltage detection level Vdet0_0
(2)
1.80 1.90 2.05 V
Voltage detection level Vdet0_1
(2)
2.15 2.35 2.50 V
Voltage detection level Vdet0_2
(2)
2.70 2.85 3.05 V
Voltage detection level Vdet0_3
(2)
3.55 3.80 4.05 V
—
Voltage detection 0 circuit response time
(4)
At the falling of Vcc from 5 V to
(Vdet0_0
− 0.1) V
— 6 150
µs
— Voltage detection circuit self power consumption VCA25 = 1, Vcc = 5.0 V — 1.5 —
µA
t
d(E-A) Waiting time until voltage detection circuit
operation starts
(3)
— — 100 µs
Table 5.7 Voltage Detection 1 Circuit Electrical Characteristics
Symbol Parameter Condition
Standard
Unit
Min. Typ. Max.
V
det1
Voltage detection level Vdet1_0
(2)
At the falling of Vcc 2.00 2.20 2.40 V
Voltage detection level Vdet1_1
(2)
At the falling of Vcc 2.15 2.35 2.55 V
Voltage detection level Vdet1_2
(2)
At the falling of Vcc 2.30 2.50 2.70 V
Voltage detection level Vdet1_3
(2)
At the falling of Vcc 2.45 2.65 2.85 V
Voltage detection level Vdet1_4
(2)
At the falling of Vcc 2.60 2.80 3.00 V
Voltage detection level Vdet1_5
(2)
At the falling of Vcc 2.75 2.95 3.15 V
Voltage detection level Vdet1_6
(2)
At the falling of Vcc 2.85 3.10 3.40 V
Voltage detection level Vdet1_7
(2)
At the falling of Vcc 3.00 3.25 3.55 V
Voltage detection level Vdet1_8
(2)
At the falling of Vcc 3.15 3.40 3.70 V
Voltage detection level Vdet1_9
(2)
At the falling of Vcc 3.30 3.55 3.85 V
Voltage detection level Vdet1_A
(2)
At the falling of Vcc 3.45 3.70 4.00 V
Voltage detection level Vdet1_B
(2)
At the falling of Vcc 3.60 3.85 4.15 V
Voltage detection level Vdet1_C
(2)
At the falling of Vcc 3.75 4.00 4.30 V
Voltage detection level Vdet1_D
(2)
At the falling of Vcc 3.90 4.15 4.45 V
Voltage detection level Vdet1_E
(2)
At the falling of Vcc 4.05 4.30 4.60 V
Voltage detection level Vdet1_F
(2)
At the falling of Vcc 4.20 4.45 4.75 V
— Hysteresis width at the rising of Vcc in voltage
detection 1 circuit
Vdet1_0 to Vdet1_5 selected — 0.07 — V
Vdet1_6 to Vdet1_F selected — 0.10 — V
—
Voltage detection 1 circuit response time
(3)
At the falling of Vcc from 5 V to
(Vdet1_0
− 0.1) V
— 60 150
µs
— Voltage detection circuit self power consumption VCA26 = 1, Vcc = 5.0 V — 1.7 —
µA
t
d(E-A) Waiting time until voltage detection circuit
operation starts
(4)
— — 100 µs
R8C/33T Group 5. Electrical Characteristics
R01DS0046EJ0110 Rev.1.10 Page 33 of 47
Apr 26, 2011
Notes:
1. The measurement condition is Vcc = 1.8 V to 5.5 V and Topr =
−20°C to 85°C (N version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes V
det2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Notes:
1. The measurement condition is Topr =
−20°C to 85°C (N version), unless otherwise specified.
2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
Figure 5.3 Power-on Reset Circuit Electrical Characteristics
Table 5.8 Voltage Detection 2 Circuit Electrical Characteristics
Symbol Parameter Condition
Standard
Unit
Min. Typ. Max.
V
det2 Voltage detection level Vdet2_0 At the falling of Vcc 3.70 4.00 4.30 V
— Hysteresis width at the rising of Vcc in voltage
detection 2 circuit
—0.10— V
—
Voltage detection 2 circuit response time
(2)
At the falling of Vcc from 5 V to
(Vdet2_0
− 0.1) V
— 20 150
µs
— Voltage detection circuit self power consumption VCA27 = 1, Vcc = 5.0 V — 1.7 —
µA
t
d(E-A) Waiting time until voltage detection circuit
operation starts
(3)
— — 100 µs
Table 5.9 Power-on Reset Circuit
(2)
Symbol Parameter Condition
Standard
Unit
Min. Typ. Max.
t
rth External power Vcc rise gradient (Note 1) 0 — 50000 mV/msec
Notes:
1. V
det0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit of User’s Manual: Hardware for details.
2. t
w(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain
t
w(por) for 1 ms or more.
Vdet0
(1)
0.5 V
Internal
reset signal
t
w(por)
(2)
Voltage detection 0
circuit response time
V
det0
(1)
1
f
OCO-S
× 32
1
f
OCO-S
× 32
External
Power V
CC
trth
trth
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R5F21336TNFP#50

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Buy R5F21336TNFP#50
Manufacturer:
Renesas Electronics
Description:
16-bit Microcontrollers - MCU R8/C33T 32+4K 1.8/5.5V -20TO85 32LQFP TR
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