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TDF8599ATH/N2/S6CY

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54
TDF8599A_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 30 June 2009 19 of 54
NXP Semiconductors
TDF8599A
I
2
C-bus controlled dual channel class-D power amplifier
The capacitor connected to pin SEL_MUTE (see Figure 3 on page 6) is used to create an
inaudible current test pulse, drawn from the positive amplifier output. The diagnostic
‘speaker load’ (or ‘open load’), based on the voltage difference between pins OUTxP and
OUTxN is shown in Figure 18.
Remark: DC load detection identifies a short circuited speaker as a valid speaker load.
OCP detection, using byte DB1[D3] for channel 1 and byte DB2[D3] for channel 2,
performs diagnostics on shorted loads. However, the diagnostics are performed after the
DC load detection cycle has finished and once the amplifier is in Operating mode.
The result of the DC load detection is stored in bits DB1[D4] and DB2[D4].
Fig 16. DC load detection circuit
Fig 17. DC load detection procedure
Fig 18. DC load detection limits
001aai787
PWM
CONTROL
DRIVER
HIGH
V
P
PGND1
OUTN
OUTP
R
L
B
DRIVER
LOW
PWM
CONTROL
DRIVER
HIGH
V
P
PGND2
DRIVER
LOW
001aai788
out (V)
t
det(DCload)
t
d(stb-mute)
t (s)
out−
out+
001aaj956
0 Ω 25 Ω 350 Ω
SPEAKER LOAD OPEN LOAD
TDF8599A_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 30 June 2009 20 of 54
NXP Semiconductors
TDF8599A
I
2
C-bus controlled dual channel class-D power amplifier
Remark: After DC load detection has been performed, the DC load valid bit DB1[D6] must
be set. The DC load data bits are only valid when bit DB1[D6] = 1. When DC load
detection is interrupted by a sudden large change in supply voltage (triggered by UVP or
OVP) or if the amplifier hangs up, the DC load valid bit is reset to DB1[D6] = 0. The DC
load detection enable bit IB2[D2] must be reset after the DC load protection cycle to
release any amplifier hang-up. Once the DC load detection cycle has finished, DC load
detection can be restarted by toggling the DC load detection enable bit IB2[D2]. However,
this can only be used if both amplifier channels have not been enabled with bit IB1[D1] or
bit IB2[D1]. See Section 8.6.2.2 “Recommended start-up sequence with DC load
detection enabled” for detailed information.
8.6.2.2 Recommended start-up sequence with DC load detection enabled
The flow diagram (Figure 19) illustrates the TDF8599A’s ability to perform a DC load
detection without starting the amplifiers. After a DC load detection cycle finishes without
setting the DC load valid bit DB1[D6], DC load detection is repeated (when bit IB2[D2] is
toggled).
To limit the maximum number of DC load detection cycle loops, a counter and limit have
been added. The loop exits after the predefined number of cycles (COUNTMAX), if the
DC load detection cycle finishes with an invalid detection.
Depending on the application needs, the invalid DC load detection cycle can be handled
as follows:
• the amplifier can be started without DC load detection
• the DC load detection loop can be executed again
Table 12. Interpretation of DC load detection bits
DC load bits DB1[D4] and DB2[D4] OCP bits DB1[D3] and DB2[D3] Description
0 0 speaker load
0 1 shorted load
1 0 open load
TDF8599A_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 30 June 2009 21 of 54
NXP Semiconductors
TDF8599A
I
2
C-bus controlled dual channel class-D power amplifier
8.6.2.3 AC load detection
AC load detection is only available in I
2
C-bus mode and is controlled using bit IB3[D4].
The default setting for bit IB3[D4] = 0 disables AC load detection. When AC load detection
is enabled (bit IB3[D4] = 1), the amplifier load current is measured and compared with a
reference level. Pin CLIP is activated when this threshold is reached. Using this
information, AC load detection can be performed using a predetermined input signal
frequency and level. The frequency and signal level should be chosen so that the load
current exceeds the programmed current threshold when the AC coupled load (tweeter) is
present.
8.6.2.4 CLIP detection
CLIP detection gives information for clip levels ≥ 0.2 %. Pin CLIP is used as the output for
the clip detection circuitry on both channel 1 and channel 2. Setting either bit IB1[D5] or bit
IB2[D5] to logic 0 defines which channel reports clip information on the CLIP pin.
Fig 19. Recommended start-up sequence with DC load detection enabled
001aaj061
NO
NO
YES
YES
restart
DC load
start amplifier
anyway
I
2
C-bus TX
IB1[D0] = 1 startup
IB2[D2] = 1 enable DC load
IB1[D1] = 1 disable channel 1
IB2[D1] = 1 disable channel 2
I
2
C-bus RX
DB1[D4] = 1 channel 1 open load
DB2[D4] = 1 channel 2 open load
DB1[D6] = 1 DC load valid
I
2
C-bus TX
IB1[D0] = 1 startup
IB2[D2] = 0 disable DC load
IB1[D1] = 0 enable channel 1
IB2[D1] = 0 enable channel 2
I
2
C-bus TX
IB1[D0] = 1 startup
IB2[D2] = 0 disable DC load
IB1[D1] = 1 disable channel 1
IB2[D1] = 1 disable channel 2
I
2
C-bus TX
IB1[D0] = 1 startup
IB2[D2] = 1 enable DC load
IB1[D1] = 1 disable channel 1
IB2[D1] = 1 disable channel 2
ERROR HANDLING
COUNT = 0
WAIT DC load
COUNT = COUNT + 1
DB1[D6] = 1
DC load valid
COUNT ≤ COUNTMAX
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54

TDF8599ATH/N2/S6CY

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Manufacturer:
NXP Semiconductors
Description:
IC POWER AMP CLASS D I2C 36HSOP
Lifecycle:
New from this manufacturer.
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