TDF8599A_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 30 June 2009 52 of 54
continued >>
NXP Semiconductors
TDF8599A
I
2
C-bus controlled dual channel class-D power amplifier
22. Tables
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 4. I
2
C-bus mode operation . . . . . . . . . . . . . . . . . . .7
Table 5. Non-I
2
C-bus mode operation . . . . . . . . . . . . . . .7
Table 6. Mode setting pin OSCIO . . . . . . . . . . . . . . . . . .7
Table 7. Oscillator modes . . . . . . . . . . . . . . . . . . . . . . .10
Table 8. Operation mode selection with the MOD pin . .11
Table 9. Overview of protection types . . . . . . . . . . . . . .15
Table 10. Overview of TDF8599A protection circuits
and amplifier states . . . . . . . . . . . . . . . . . . . . .17
Table 11. Available data on pins DIAG and CLIP . . . . . .18
Table 12. Interpretation of DC load detection bits . . . . . .20
Table 13. I
2
C-bus write address selection using
pins MOD and ADS . . . . . . . . . . . . . . . . . . . . . 23
Table 14. Instruction byte descriptions . . . . . . . . . . . . . . 25
Table 15. Phase shift bit settings . . . . . . . . . . . . . . . . . .25
Table 16. Description of data bytes . . . . . . . . . . . . . . . . . 26
Table 17. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 18. Thermal characteristics . . . . . . . . . . . . . . . . . . 28
Table 19. Static characteristics . . . . . . . . . . . . . . . . . . . .28
Table 20. Switching characteristics . . . . . . . . . . . . . . . . .31
Table 21. Dynamic characteristics . . . . . . . . . . . . . . . . .32
Table 22. Filter component values . . . . . . . . . . . . . . . . .36
Table 23. SnPb eutectic process (from J-STD-020C) . . .48
Table 24. Lead-free process (from J-STD-020C) . . . . . . 48
Table 25. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 26. Revision history . . . . . . . . . . . . . . . . . . . . . . . .50
23. Figures
Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Fig 2. Heatsink up (top view) pin configuration
TDF8599ATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Fig 3. Mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Fig 4. Clock frequency as a function of R
osc
. . . . . . . . . .8
Fig 5. Master and slave configuration . . . . . . . . . . . . . . .8
Fig 6. Spread spectrum mode . . . . . . . . . . . . . . . . . . . . .9
Fig 7. Spread spectrum operation in Master mode . . . . .9
Fig 8. Phase lock operation . . . . . . . . . . . . . . . . . . . . . .10
Fig 9. AD/BD modulation switching circuit . . . . . . . . . . .12
Fig 10. AD modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Fig 11. BD modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Fig 12. Master and slave operation with
1
⁄
2
p phase
shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Fig 13. Parallel mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Fig 14. DC offset protection and diagnostic output . . . . .16
Fig 15. Diagnostic output for short circuit conditions . . . .18
Fig 16. DC load detection circuit . . . . . . . . . . . . . . . . . . .19
Fig 17. DC load detection procedure . . . . . . . . . . . . . . . .19
Fig 18. DC load detection limits . . . . . . . . . . . . . . . . . . . .19
Fig 19. Recommended start-up sequence with DC
load detection enabled. . . . . . . . . . . . . . . . . . . . .21
Fig 20. Start-up and shutdown timing in I
2
C-bus
mode with DC load detection. . . . . . . . . . . . . . . .22
Fig 21. Start-up and shutdown timing in non-I
2
C-bus
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Fig 22. I
2
C-bus start and stop conditions. . . . . . . . . . . . .24
Fig 23. Data bits sent from Master microprocessor
(Mmp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Fig 24. I
2
C-bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Fig 25. I
2
C-bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Fig 26. P
o
as a function of V
P
in stereo mode with
THD = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Fig 27. P
o
as a function of V
P
in stereo mode with
THD = 10 %. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Fig 28. P
o
as a function of V
P
in parallel mode with
THD = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Fig 29. P
o
as a function of V
P
parallel mode with
THD = 10 %. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Fig 30. THD + N as a function of output power
with a 2 W load; V
P
= 14.4 V . . . . . . . . . . . . . . . . 37
Fig 31. THD + N as a function of output power
with a 4 W load; V
P
= 14.4 V . . . . . . . . . . . . . . . . 37
Fig 32. THD + N as a function of output power
with a 2 W load; V
P
= 35 V . . . . . . . . . . . . . . . . . 38
Fig 33. THD + N as a function of output power
with a 4 W load; V
P
= 35 V . . . . . . . . . . . . . . . . . 38
Fig 34. THD + N as a function of frequency
with a 2 W load, BD modulation; V
P
= 14.4 V . . . 38
Fig 35. THD + N as a function of frequency
with a 4 W load, BD modulation; V
P
= 14.4 V . . . 38
Fig 36. THD + N as a function of frequency
with a 2 W load, BD modulation; V
P
= 35 V. . . . . 39
Fig 37. Gain as a function of frequency. . . . . . . . . . . . . . 39
Fig 38. Output power as a function of supply voltage
with a 2 W load . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Fig 39. Output power as a function of supply voltage
with a 4 W load . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Fig 40. Channel separation as a function of frequency
with 1 W output power. . . . . . . . . . . . . . . . . . . . . 40
