TDF8599A_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 30 June 2009 22 of 54
NXP Semiconductors
TDF8599A
I
2
C-bus controlled dual channel class-D power amplifier
8.6.3 Start-up and shutdown sequence
To prevent switch on or switch off ‘pop noises’, a capacitor (C
SVRR
) connected to pin
SVRR is used to smooth start-up and shutdown. During start-up and shutdown, the output
voltage tracks the voltage on pin SVRR. Increasing C
SVRR
results in a longer start-up and
shutdown time. Enhanced pop noise performance is achieved by muting the amplifier until
the SVRR voltage reaches its final value and the outputs start switching. The capacitor
value on pin SEL_MUTE (C
ON
) determines the unmute and mute timing. The voltage on
pin SEL_MUTE determines the amplifier gain. Increasing C
ON
increases the unmute and
mute times. In addition, a larger C
ON
value increases the DC load detection cycle.
When the amplifier is switched off with an I
2
C-bus command or by pulling pin EN LOW, the
amplifier is first muted and then capacitor (C
SVRR
) is discharged.
In Slave mode, the device enters the off state immediately after capacitor (C
SVRR
) is
discharged. In Master mode, the clock is kept active by an additional delay (t
d
(2)
) of
approximately 50 ms to allow slave devices to enter the off state.
When an external clock is connected to pin OSCIO (in Slave mode), the clock must
remain active during the shutdown sequence for delay (t
d
(1)
) to ensure that the slaved
TDF8599A devices are able to enter the off state.
(1) Shutdown hold delay.
(2) Master mode shutdown delay.
(3) Shutdown delay.
Fig 20. Start-up and shutdown timing in I
2
C-bus mode with DC load detection
001aai790
V
DDA
DIAG
EN
ACGND
IB1[D0] and
IB2[D0] = 0
SEL_MUTE
SVRR
OUTn
t
d
(2)
t
d
(1)
t
d(mute-fgain)
mute delay
t
d(stb-mute)
t
wake
t
det(DCload)
t
d
(3)
