TDF8599A_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 30 June 2009 43 of 54
NXP Semiconductors
TDF8599A
I
2
C-bus controlled dual channel class-D power amplifier
Dual BTL mode (stereo) in I
2
C-bus mode with DC offset protection enabled, Spread spectrum
mode disabled.
(1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 8 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.
Fig 48. Example application diagram: dual BTL in I
2
C-bus mode
001aak081
22
39 k
10 k
10 k
13 k
10
10
22
100 µF
35 V
100 µF
35 V
100 nF
15 nF
470 nF
100 nF
15 nF
470 pF 470 pF
470 pF
470 pF
C
LC
C
IN1P
470 nF
C
IN1N
470 nF
C
IN2P
470 nF
470 nF
2.2 µF
47 µF
C
IN2N
L
LC
L
LC
C
LC
100 nF
PGND1
PGND1
V
P1
V
P1
V
P1
V
P2
V
PA
TDF8599A
bead
bead
R
ADS
bead
bead
OUT1N
OUT1P
OUT1N
V
P
GND
OUT1P
VSTAB1
GNDD/HW
33
32
31
30
29
28
34
35
36
25
24
23
22
21
20
19
26
27
4
5
6
7
8
9
3
2
1
12
13
14
15
16
17
18
11
10
BOOT1N
BOOT1P
V
P1
PGND1
PGND1
PGND2
V
DDD
1000 µF
35 V
4.7 µF
100 nF
220 nF
VSTAB2
DCP
OSCIO
220 nF
22
10
10
22
100 nF
15 nF
100 nF
15 nF
470 pF 470 pF
470 pF
470 pF
C
LC
L
LC
L
LC
C
LC
100 nF
PGND2
PGND2
V
P2
V
P2
OUT2P
OUT2N
OUT2P
OUT2N
BOOT2P
BOOT2N
V
P2
PGND2
IN2N
AGND
IN2P
IN1P
ACGND
SVRR
EN
SEL_MUTE
(1)
IN1N
IN2N
100 nF
100 nF
(2)
C
ACGND
enable
(1)
IN2P
IN1P
IN1N
SCL
SSM
OSCSET
V
DDA
SDA
V
Pull-up
V
Pull-up
V
PA
stereo mode
setting
connect
to µP
MASTER
MODE
I
2
C-bus
address select
ADS
DIAG
MOD
CLIP
(3)
TDF8599A_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 30 June 2009 44 of 54
NXP Semiconductors
TDF8599A
I
2
C-bus controlled dual channel class-D power amplifier
Single BTL mode (parallel) in I
2
C-bus mode with DC offset protection enabled, Spread spectrum
mode disabled.
(1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 8 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.
Fig 49. Example application diagram: single BTL in I
2
C-bus mode
001aak082
22
39 k
10 k
10 k
33 k
10
10
22
100 µF
35 V
100 µF
35 V
100 nF
15 nF
470 nF
100 nF
15 nF
470 pF 470 pF
470 pF
470 pF
C
LC
C
INP
470 nF
C
INN
470 nF
2.2 µF
47 µF
L
LC
L
LC
C
LC
100 nF
PGND1
PGND1
V
P1
V
P1
V
P1
V
P2
V
PA
TDF8599A
bead
bead
R
ADS
bead
bead
OUT1N
OUT1P
OUTN
V
P
GND
OUTP
VSTAB1
GNDD/HW
33
32
31
30
29
28
34
35
36
25
24
23
22
21
20
19
26
27
4
5
6
7
8
9
3
2
1
12
13
14
15
16
17
18
11
10
BOOT1N
BOOT1P
V
P1
PGND1
PGND1
PGND2
V
DDD
1000 µF
35 V
4.7 µF
100 nF
220 nF
VSTAB2
DCP
OSCIO
220 nF
10
10
15 nF
100 nF
15 nF
470 pF 470 pF
470 pF
470 pF
L
LC
L
LC
PGND2
PGND2
V
P2
V
P2
OUT2P
OUT2N
BOOT2P
BOOT2N
V
P2
PGND2
IN2N
AGND
IN2P
IN1P
ACGND
SVRR
EN
SEL_MUTE
(1)
IN1N
100 nF
100 nF
C
ACGND
enable
(1)
INP
INN
SCL
SSM
OSCSET
V
DDA
SDA
V
Pull-up
V
Pull-up
V
PA
parallel mode
setting
connect
to µP
fixed
frequency
(2)
MASTER
MODE
I
2
C-bus
address select
ADS
DIAG
MOD
CLIP
(3)
TDF8599A_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 30 June 2009 45 of 54
NXP Semiconductors
TDF8599A
I
2
C-bus controlled dual channel class-D power amplifier
I
2
C-bus mode: dual BTL in Master mode, one BTL in Slave mode; DC offset protection enabled.
(1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 8 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on disabling DC offset protection.
(4) See Section 8.3.4 on page 10 for detailed information on PLL operation.
Fig 50. Example application diagram: dual BTL master, single BTL slave in I
2
C-bus mode
22
39 k20 k
10 k
10 k
13 k
10
10
22
100 µF
35 V
100 µF
35 V
100 nF
15 nF
470 nF
100 nF
15 nF
470 pF 470 pF
470 pF
470 pF
C
LC
C
IN1P
470 nF
C
IN1N
470 nF
C
IN2P
470 nF
470 nF
2.2 µF
47 µF
1 µF
C
IN2N
L
LC
L
LC
C
LC
100 nF
PGND1
PGND1
V
P1
V
P1
V
P1
V
P2
V
PA
TDF8599A
bead
bead
R
ADS
bead
bead
OUT1N
OUT1P
OUT1N
V
P
GND
OUT1P
VSTAB1
GNDD/HW
33
32
31
30
29
28
34
35
36
25
24
23
22
21
20
19
26
27
4
5
6
7
8
9
3
2
1
12
13
14
15
16
17
18
11
10
BOOT1N
BOOT1P
V
P1
PGND1
PGND1
PGND2
V
DDD
1000 µF
35 V
4.7 µF
100 nF
220 nF
VSTAB2
DCP
OSCIO
220 nF
22
10
10
22
100 nF
15 nF
100 nF
15 nF
470 pF 470 pF
470 pF
470 pF
C
LC
L
LC
L
LC
C
LC
100 nF
PGND2
PGND2
V
P2
V
P2
OUT2P
MASTER
SLAVE
OUT2N
OUT2P
OUT2N
BOOT2P
BOOT2N
V
P2
PGND2
IN2N
AGND
IN2P
IN1P
ACGND
SVRR
EN
(1)
SEL_MUTE
(1)
IN1N
IN2N
100 nF
100 nF
C
ACGND
enable
IN2P
IN1P
IN1N
SCL
SSM
OSCSET
V
DDA
SDA
V
PAPull-up
V
Pull-up
V
PA
stereo mode
setting
spread
spectrum
mode
(2)
DC offset
protection enabled
(3)
DC offset
protection enabled
(3)
MASTER
MODE
I
2
C-bus
address select
ADS
DIAG
MOD
CLIP
001aak083
22
5.1 k
10 k
10 k
33 k
10
10
22
100 nF
15 nF
470 nF
100 nF
15 nF
470 pF 470 pF
470 pF
470 pF
C
LC
C
INP
470 nFC
INN
470 nF
2.2 µF
47 µF
L
LC
L
LC
C
LC
100 nF
PGND1
PGND1
V
P1
V
P1
TDF8599A
bead
R
ADS
OUT1N
OUT1P
OUT3N
OUT3P
VSTAB1
GNDD/HW
33
32
31
30
29
28
34
35
36
25
24
23
22
21
20
19
26
27
4
5
6
7
8
9
3
2
1
12
13
14
15
16
17
18
11
10
BOOT1N
BOOT1P
V
P1
PGND1
V
DDD
4.7 µF
100 nF
220 nF
VSTAB2
DCP
OSCIO
220 nF
10
10
15 nF
100 nF
15 nF
470 pF 470 pF
470 pF
470 pF
L
LC
L
LC
PGND2
PGND2
V
P2
V
P2
OUT2P
OUT2N
BOOT2P
BOOT2N
V
P2
PGND2
IN2N
AGND
IN2P
IN1P
ACGND
SVRR
EN
(1)
SEL_MUTE
(1)
IN1N
100 nF
10 nF
270 nF
C
ACGND
IN3P
IN3N
SCL
SSM
OSCSET
V
DDA
SDA
V
Pull-up
V
Pull-up
V
PA
parallel mode
setting
connect
to µP
phase lock
operation
(4)
SLAVE MODE
I
2
C-bus
address select
ADS
DIAG
MOD
CLIP

TDF8599ATH/N2/S6CY

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC POWER AMP CLASS D I2C 36HSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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