X9268TS24IZ-2.7T1 Datasheet X9268TS24IZ-2.7, X9268US24IZ, X9268TS24IZT1 | P7-P9

FN8172.4

August 29, 2006

SERIAL INTERFACE DESCRIPTION

Serial Interface

The X9268 supports a bidirectional bus oriented

protocol. The protocol defines any device that sends

data onto the bus as a transmitter and the receiving

device as the receiver. The device controlling the

transfer is a master and the device being controlled is

the slave. The master will always initiate data transfers

and provide the clock for both transmit and receive

operations. Therefore, the X9268 will be considered a

slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW periods. SDA state changes during SCL

HIGH are reserved for indicating start and stop

conditions. See Figure 2.

Start Condition

All commands to the X9268 are preceded by the start

condition, which is a HIGH to LOW transition of SDA

while SCL is HIGH. The X9268 continuously monitors

the SDA and SCL lines for the start condition and will

not respond to any command until this condition is

met. See Figure 2.

Stop Condition

All communications must be terminated by a stop

condition, which is a LOW to HIGH transition of SDA

while SCL is HIGH. See Figure 2.

Acknowledge

Acknowledge is a software convention used to provide

a positive handshake between the master and slave

devices on the bus to indicate the successful receipt of

data. The transmitting device, either the master or the

slave, will release the SDA bus after transmitting eight

bits. The master generates a ninth clock cycle and

during this period the receiver pulls the SDA line LOW

to acknowledge that it successfully received the eight

bits of data.

The X9268 will respond with an acknowledge after

recognition of a start condition and its slave address

and once again after successful receipt of the

command byte. If the command is followed by a data

byte the X9268 will respond with a final acknowledge.

See Figure 2.

Figure 2. Acknowledge Response from Receiver

SCL FROM

MASTER

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

X9268

FN8172.4

August 29, 2006

Acknowledge Polling

The disabling of the inputs, during the internal

nonvolatile write operation, can be used to take

advantage of the typical 5ms nonvolatile write cycle

time. Once the stop condition is issued to indicate the

end of the nonvolatile write command the X9268

initiates the internal write cycle. ACK polling, Flow 1,

can be initiated immediately. This involves issuing the

start condition followed by the device slave address. If

the X9268 is still busy with the write operation no ACK

will be returned. If the X9268 has completed the write

operation an ACK will be returned and the master can

then proceed with the next operation.

FLOW 1: ACK Polling Sequence

INSTRUCTION AND REGISTER DESCRIPTION

Instructions

EVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A)

The first byte sent to the X9268 from the host is called

the Identification Byte. The most significant four bits of

the slave address are a device type identifier. The

ID[3:0] bits is the device id for the X9268; this is fixed

as 0101[B] (refer to Table 1).

The A[3:0] bits in the ID byte is the internal slave

address. The physical device address is defined by

the state of the A3 - A0 input pins. The slave address

is externally specified by the user. The X9268

compares the serial data stream with the address

input state; a successful compare of both address

bits is required for the X9268 to successfully continue

the command sequence. Only the device which slave

address matches the incoming device address sent

by the master executes the instruction. The A3 - A0

inputs can be actively driven by CMOS input signals

or tied to V

or V

NSTRUCTION BYTE (I)

The next byte sent to the X9268 contains the

instruction and register pointer information. The three

most significant bits are used provide the instruction

opcode I [3:0]. The RB and RA bits point to one of the

four Data Registers of each associated XDCP. The

least significant bit points to one of two Wiper Counter

Registers or Pots. The format is shown in Table 2.

Nonvolatile Write

Command Completed

EnterACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Further

Operation?

Issue

Instruction

Issue STOP

Yes

Proceed

Issue STOP

Proceed

DR0 0 0

DR1 0 1

DR2 1 0

DR3 1 1

X9268

FN8172.4

August 29, 2006

Table 1. Identification Byte Format

Table 2. Instruction Byte Format

Table 3. Instruction Set

Note: 1/0 = data is one or zero

Instruction

Instruction Set

OperationI3 I2 I1 I0 RB RA 0 P0

Read Wiper Counter

100100 01/0Read the contents of the Wiper Counter

Write Wiper Counter Register 101000 01/0Write new value to the Wiper Counter

Read Data Register 10111/01/001/0Read the contents of the Data Register

pointed to by P0 and RB - RA

Write Data Register 11001/01/001/0Write new value to the Data Register

pointed to by P0 and RB - RA

XFR Data Register to Wiper

Counter Register

11011/01/001/0Transfer the contents of the Data Register

pointed to by P0 and RB - RA to its

associated Wiper Counter Register

XFR Wiper Counter Register

to Data Register

11101/01/001/0Transfer the contents of the Wiper Counter

Global XFR Data Registers to

Wiper Counter Registers

00011/01/00 0Transfer the contents of the Data Registers

pointed to by RB - RA of all four pots to their

respective Wiper Counter Registers

Global XFR Wiper Counter

Registers to Data Register

10001/01/00 0Transfer the contents of both Wiper Counter

Registers to their respective data Registers

pointed to by RB - RA of all four pots

Increment/Decrement Wiper

Counter Register

001000 01/0Enable Increment/decrement of the Control

Latch pointed to by P0

ID3 ID2 ID1 ID0 A3 A2 A1 A0

0101

(MSB) (LSB)

Device Type

Identifier

Slave Address

I3 I2 I1 I0 RB RA 0 P0

(MSB) (LSB)

Instruction

Pot Selection

Opcode

Selection

(WCR Selection)

Data

X9268

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

X9268TS24IZ-2.7T1

Mfr. #:

Buy X9268TS24IZ-2.7T1

Manufacturer:

Renesas / Intersil

Description:

Digital Potentiometer ICs DL DCP 100KOHM 256 TAPS 2-WIRE

Lifecycle:

New from this manufacturer.

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X9268TS24IZ-2.7T1

X9268TS24IZ-2.7T1

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