15©2016 Integrated Device Technology, Inc Revision A April 28, 2016
844S42I Data Sheet
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 844S42I provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V
DD,
V
DDA,
V
DDOA
and V
DDOB
should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic V
DD
pin and also shows that V
DDA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the V
DDA
pin.
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups or pulldowns;
additional resistance is not required but can be added
for additional protection. A 1k resistor can be used.
Crystal Inputs
For applications not requiring the use of the crystal
oscillator input, both XTAL_IN and XTAL_OUT can be
left floating. Though not required, but for additional
protection, a 1k resistor can be tied from XTAL_IN to
ground.
REF_CLK Input
For applications not requiring the use of the reference
clock, it can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from the
REF_CLK to ground.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of
the differential output pair should either be left floating or
terminated.
LVDS Outputs
All unused LVDS output pairs can be either left floating
or terminated with 100 across. If they are left floating,
we recommend that there is no trace attached.
V
DD
V
DDA
3.3V
10
Ω
10µF.01µF
.01µF
