844S42BKILF Datasheet 844S42BKILF, 844S42BKILFT | P7-P9

844S42I Data Sheet

Programming the 844S42I

The 844S42I has a parallel and a serial configuration interface. The

purpose of the parallel interface is to directly configure the PLL

dividers through hardware pins without the overhead of a serial

protocol. At device startup, the device always obtains an initial PLL

frequency configuration through the parallel interface. The parallel

interface does not support reading the PLL configuration. The serial

interface is I

C compatible. It allows reading and writing devices

settings by accessing internal device registers. The serial interface is

designed for host-controller access to the synthesizer frequency

settings, for instance, in frequency-margining applications.

Using the Parallel Interface

The parallel interface supports write-access to the PLL frequency

setting directly through 17 configuration pins (P, M[9:0], NA[2:0], and

NB[2:0]). The parallel interface must be enabled by setting nPLOAD

to logic low level. During nPLOAD = 0, any change of the logical

state of the P, M[9:0], NA[2:0] and NB[2:0] pins will immediately

affect the internal PLL divider settings, resulting in a change of the

internal VCO frequency and the output frequency. The parallel

interface mode disables the I

C write-access to the internal

registers; however, I

C read-access to the internal configuration

registers is enabled. Upon startup, when the device reset signal is

released (rising edge of the nMR signal), the device reads its startup

configuration through the parallel interface and independent of the

state of nPLOAD. It is recommended to provide a valid PLL

configuration for startup. If the parallel interface pins are left open, a

default PLL configuration will be loaded. After the low-to-high

transition of nPLOAD, the configuration pins have no more effect and

the configuration registers are made accessible through the serial

interface.

Table 3D. PLL Feedback Divider (M) Configuration Table

Table 3E. PLL Post-Divider (NA) Configuration Table

Table 3F. PLL Post-Divider (NB) Configuration Table

Table 3G. PLL Pre-Divider (P) Configuration Table

M Bits9876543210

Pin M9 M8 M7 M6 M5 M4 M3 M2 M1 M0

Default1001110001

NA Bits 2 1 0

Pin NA2 NA1 NA0

Default 0 0 0

NB Bits 2 1 0

Pin NB2 NB1 NB0

Default 0 0 0

Pin P

Default 1

844S42I Data Sheet

Using the I

C Interface

nPLOAD = 1 enables the programming and monitoring of the

internal registers through the I

C interface. Device register access

(write and read) is possible through the 2-wire interface using SDA

(configuration data) and SCL (configuration clock) signals. The

844S42I acts as a slave device at the I

C bus. For further information

on I

C it is recommended to refer to the I

C bus specification

(version 2.1).

nPLOAD = 0 disables the I

C-write-access to the configuration

registers and any data written into the register is ignored. However,

the 844S42I is still visible at the I

C interface and I

C transfers are

acknowledged by the device. Read-access to the internal registers

during nPLOAD = 0 (parallel programming mode) is supported. Note

that the device automatically obtains a configuration using the

parallel interface upon the release of the device reset (rising edge of

nMR) and independent on the state of nPLOAD. Changing the state

of the nPLOAD input is not supported when the device performs any

transactions on the I

C interface.

Programming Model and Register Set

The synthesizer contains three fully accessible configuration

registers (0x00 through 0x02). Programming the synthesizer

frequency through the I

C interface is a one step process at which all

registers are written at once by a single I

C transaction. The PLL

frequency is affected as a result of the completion of the entire three

configuration registers are read as a single I

C transaction. All

registers are read back-to-back. Note that the synthesizer does not

check any boundary conditions such as the VCO frequency range.

Writing the PLL registers could result in invalid VCO frequencies

(VCO frequency beyond lock range).

It is always required to configure the entire 844S42I register file

(0x00, 0x01, 0x02), addressing single register bytes is not

supported. Writing any information to the bits 2, 1 and 0 in register

0x02 is ignored. These bits indicate information updated by the

synthesizer (bit 2 is the PLL lock status, bits 1 and 0 are copies of the

ADR[1:0] pin status).

Table 3H. Register File Table

C Register Access in Parallel Mode

The 844S42I supports the configuration of the synthesizer through

the parallel interface (nPLOAD = 0) and serial interface (nPLOAD =

1). Register contents and the divider configurations are not changed

when the user switches from parallel mode to serial mode. However,

when switching from serial mode to parallel mode, the PLL dividers

immediately reflect the logical state of the hardware pins M[9:0],

NA[2:0], NB[2:0], and P. Applications using the parallel interface to

obtain a PLL configuration can use the serial interface to verify the

divider settings. In parallel mode (nPLOAD = 0), the 844S42I allows

read-access to the registers through I

C (if nPLOAD = 0), the current

PLL configuration is stored in the registers. After changing from

parallel to serial mode (nPLOAD = 1), the last PLL configuration is

still stored in the registers. The user now has full write and read

access to both configuration registers through the I

C bus and can

change the configuration at any time.

0x00H M7 M6 M5 M4 M3 M2 M1 M0 R/W

Default 01110001

0x01H M9 M8 NA2 NA1 NA0 NB2 NB1 NB0 R/W

Default 10000000

0x02H P RES RES RES RES LOCK ADR1 ADR0 R/W

Default 10000000

844S42I Data Sheet

Programming the I

C Interface

Table 3I. I

C Slave Address Table

The 844S42I acts as a slave device at the I

C bus. The register file

is reset to its default values at power-up by an integrated power-on

reset circuit or by applying an external device reset signal (nMR).The

7-bit I

C slave address of the 844S42I synthesizer is a combination

of a 5-bit fixed addresses and two variable bits which are set by the

hardware pins ADR[1:0]. Bit 0 of the 844S42I slave address is used

by the bus controller to select either the read or write mode. ‘0’

indicates a transmission (I

C-WRITE) to the 844S42I. “1” indicates a

request for data (I

C-READ) from the synthesizer. The hardware

pins ADR1 and ADR0 and should be individually set by the user to

avoid address conflicts of multiple 844S42I devices on the same I

bus.

Each access to the I

C register file must read or write the entire four

followed by register 0x01H, until register 0x02H. Addressing

individual bytes is not supported. The bytes will program internal

part circuitry upon receipt of all three bytes and a given I

C bus

<STOP> signal.

Device Startup

General Device Configuration: It is recommended to reset the

844S42I after the system powers up. The device acquires an initial

PLL divider configuration through the parallel interface pins M[9:0],

NA[2:0], NB[2:0] and P

NOTE1

with the low-to-high transition of

nMR

NOTE2

. PLL frequency lock is achieved within the specified lock

time (t

LOCK

) and is indicated by an assertion of the LOCK_DT signal

which completes the startup procedure. The output frequency can

be reconfigured at any time through either the parallel or the serial

interface.

Starting-Up Using the Parallel Interface

The simplest way to use the 844S42I is through the parallel

interface. The serial interface pins (SDA, SDL, and ADR[1:0]) can be

left open and nPLOAD is set to logic low. After the release of nMR

and at any other time the PLL and output frequency configuration is

directly set to through the M[9:0], NA[2:0], NB[2:0] and P pins.

Table 3J. REF_SEL Configuration Table

Table 3K. nBYPASS Configuration Table

The nBYPASS control should be set to logic LOW for normal

operation. nBYPASS = 1 enables the PLL bypass mode for factory

test. In PLL bypass mode, the output frequency is equal to the input

frequency divided by NA, NB and frequency multiplication is

disabled.

Table 3L. nMR Configuration Table

The output type and output voltage levels of both outputs are

configured through the configuration input LEV_SEL. LEV_SEL

connected to logic high results in LVPECL output levels and

LEV_SEL connected to logic low results in LVDS output levels of

both QA and QB differential outputs.

Table 3M. LEV_SEL Configuration Table

Table 3N. LOCK_DT Configuration Table

NOTE 1: The parallel interface pins M[9:0], NA[2:0], NB[2:0] and P may be left open (floating). In this case the initial PLL configuration will have the default setting

of M = 625MHz, P = 1 (÷4), NA[2:0] = 000 (÷1), NB[2:0] = 000 (÷1), resulting in an internal VCO frequency of 2500MHz (f

REF

= 16MHz) and an output frequency

of 2500MHz at both outputs.

NOTE 2: The initial PLL configuration is independent on the selected programming mode (nPLOAD low or high).

Bit 7 6 5 4 3 2 1 0

Value 1 0 1 1 0 ADR1 ADR0 R/W

REF_SEL Operation

Selects REF_CLK input as reference frequency

input

1 (default) Selects the XTAL interface as reference frequency

nBYPASS Operation

0 (default)

QA,

= ((f

REF

÷ P) * M) ÷ NA, NB

PLL operation

QA,

= f

REF

÷ NA, NB

PLL is bypassed, AC specifications do not apply

nMR Operation

The device is reset and the default settings are

loaded into the I

C file (low to high transition of nMR)

1 (default) Normal operation

LEV_SEL Operation

0 (default) QA, QB outputs are LVDS compatible

1 QA, QB outputs are LVPECL compatible

LOCK_DT Operation

0 Device is not locked to the input reference clock

1 Device is locked to the input reference clock

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

844S42BKILF

Mfr. #:

Buy 844S42BKILF

Manufacturer:

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Description:

Clock Synthesizer / Jitter Cleaner LVPECL/LVDS 2-OUT RF SYNTHESIZER

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