21©2016 Integrated Device Technology, Inc Revision A April 28, 2016
844S42I Data Sheet
Power Considerations – LVPECL Outputs
This section provides information on power dissipation and junction temperature for the 844S42I, for all outputs that are configured to LVPECL
(LEV_SEL = 1). Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 844S42I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)
MAX
= V
DD_MAX
* I
GND_MAX
= 3.465V * 260mA = 900.9mW
• Power (outputs)
MAX
= 36mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 36mW = 72mW
Total Power_
MAX
(3.465V, with all outputs switching) = 800.9mW + 72mW = 972.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 31.4°C/W per Table 7A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.973W * 31.4°C/W = 115.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7A. Thermal Resistance
JA
for 56 Lead VFQFN Forced Convection
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 31.4°C/W 27.5°C/W 24.6°C/W
