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MAX2160ETL+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
MAX2160/MAX2160EBG
ISDB-T Single-Segment Low-IF Tuners
16 ______________________________________________________________________________________
Table 10. Status Byte-1 Register
BIT NAME
BIT LOCATION
(0 = LSB)
FUNCTION
X 7, 6, 5 Unused.
CP[1:0] 4, 3 Reflect the charge-pump current setting. See Table 3 for CP[1:0] definition.
PWR 2
Logic-high indicates power has been cycled, but the device has the default programming. A STOP
condition while in read mode resets this bit.
VASA 1
Indicates whether VCO automatic selection was successful.
0 = indicates the autoselect function is disabled or unsuccessful VCO selection
1 = indicates successful VCO automatic selection
VASE 0
Status indicator for the autoselect function.
0 = indicates the autoselect function is active
1 = indicates the autoselect process is inactive
Table 11. Status Byte-2 Register
BIT NAME
BIT LOCATION
(0 = LSB)
FUNCTION
VCO[1:0] 7, 6
Indicate which VCO has been selected by either the autoselect state machine or by manual
selection when the VAS state machine is disabled. See Table 4 for VCO[1:0] definition.
VSB[2:0] 5, 4, 3
Indicate which sub-band of a particular VCO has been selected by either the autoselect state
machine or by manual selection when the VAS state machine is disabled. See Table 4 for VSB[2:0]
definition.
ADC[2:0] 2, 1, 0 Indicate the 3-bit ADC conversion of the VCO tuning voltage (VTUNE).
2-Wire Serial Interface
The MAX2160/EBG uses a 2-wire I
2
C-compatible serial
interface consisting of a serial-data line (SDA) and a
serial-clock line (SCL). SDA and SCL facilitate bidirec-
tional communication between the MAX2160/EBG and
the master at clock frequencies up to 400kHz. The
master initiates a data transfer on the bus and gener-
ates the SCL signal to permit data transfer. The
MAX2160/EBG behave as a slave device that transfers
and receives data to and from the master. SDA and
SCL must be pulled high with external pullup resistors
(1kΩ or greater) for proper bus operation.
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles is required to transfer a
byte in or out of the MAX2160/EBG (8 bits and an
ACK/NACK). The data on SDA must remain stable dur-
ing the high period of the SCL clock pulse. Changes in
SDA while SCL is high and stable are considered con-
trol signals (see the START and STOP Conditions sec-
tion). Both SDA and SCL remain high when the bus is
not busy.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high.
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the mas-
ter and the MAX2160/EBG (slave) generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse.
MAX2160/MAX2160EBG
ISDB-T Single-Segment Low-IF Tuners
______________________________________________________________________________________ 17
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data trans-
fer happens if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master must reattempt communication
at a later time.
Slave Address
The MAX2160/EBG have a 7-bit slave address that
must be sent to the device following a START condition
to initiate communication. The slave address is internal-
ly programmed to 1100000. The eighth bit (R/W) follow-
ing the 7-bit address determines whether a read or
write operation will occur.
The MAX2160/EBG continuously await a START condi-
tion followed by its slave address. When the device
recognizes its slave address, it acknowledges by
pulling the SDA line low for one clock period; it is ready
to accept or send data depending on the R/W bit
(Figure 1).
Write Cycle
When addressed with a write command, the
MAX2160/EBG allow the master to write to a single reg-
ister or to multiple successive registers.
A write cycle begins with the bus master issuing a START
condition followed by the seven slave address bits and a
write bit (R/W = 0). The MAX2160/EBG issue an ACK if
the slave address byte is successfully received. The bus
master must then send to the slave the address of the first
register it wishes to write to (see Table 1 for register
addresses). If the slave acknowledges the address, the
master can then write one byte to the register at the spec-
ified address. Data is written beginning with the most sig-
nificant bit. The MAX2160/EBG again issue an ACK if the
data is successfully written to the register. The master
can continue to write data to the successive internal reg-
isters with the MAX2160/EBG acknowledging each suc-
cessful transfer, or it can terminate transmission by
issuing a STOP condition. The write cycle will not termi-
nate until the master issues a STOP condition.
Figure 2 illustrates an example in which registers 0
through 2 are written with 0x0E, 0xD8, and 0xE1,
respectively.
SCL
SDA
123456789
S 1100000R / WACK
SLAVE ADDRESS
P
Figure 1. MAX2160 Slave Address Byte
START
WRITE DEVICE
ADDRESS
R/W
1100000 0
WRITE REGISTER
ADDRESS
0x00
ACK ACK
WRITE DATA TO
REGISTER 0x00
0x0E
ACK
WRITE DATA TO
REGISTER 0x01
0xD8
ACK
WRITE DATA TO
REGISTER 0x02
0xE1
ACK
STOP
Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8, and 0xE1, Respectively
MAX2160/MAX2160EBG
ISDB-T Single-Segment Low-IF Tuners
18 ______________________________________________________________________________________
Read Cycle
There are only two registers on the MAX2160/EBG that
are available to be read by the master. When
addressed with a read command, the MAX2160/EBG
send back the contents of both read registers (STATUS
BYTE-1 and STATUS BYTE-2).
A read cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a read bit (R/W = 1). If the slave address byte
is successfully received, the MAX2160/EBG issue an
ACK. The master then reads the contents of the STA-
TUS BYTE-1 register, beginning with the most signifi-
cant bit, and acknowledges if the byte is received
successfully. Next, the master reads the contents of the
STATUS BYTE-2 register. At this point the master can
issue an ACK or NACK and then a STOP condition to
terminate the read cycle.
Figure 3 illustrates an example in which the read regis-
ters are read by the master.
Applications Information
RF Input (RFIN)
The MAX2160/EBG are internally matched to 50Ω and
requires a DC-blocking capacitor (see the Typical
Operating Circuit).
RF Gain Control (GC1)
The MAX2160/EBG feature a variable-gain low-noise
amplifier that provides 43dB of RF gain-control range.
The voltage control (V
GC1
) range is 0.3V (minimum
attenuation) to 2.7V (maximum attenuation).
IF Power Detector
The MAX2160/EBG include a true RMS power detector
at the mixer output. The power-detector circuit is
enabled or disabled with the EPD bit in the control reg-
ister. The attack point can be set through the PD[2:0]
bits in the control register (see Table 5 for a summary
of attack point settings).
The PWRDET pin output can be configured to provide
either a voltage output (directly from the RMS power-
detector stage) or current output (default) through the
diagnostic bits D[2:0] in the test register.
Closed-Loop RF Power Control
The default mode of the IF power detector is current out-
put mode. Closed-loop RF power control is formed by
connecting the PWRDET pin directly to the GC1 pin. A
shunt capacitor to ground is added to set the closed-
loop response time (see the Typical Operating Circuit).
The recommended capacitor value of 10nF provides a
response time of 0.1ms.
Closed-loop RF power control can also be formed using
the baseband processor and the power detector in volt-
age output mode. In this configuration, the processor
senses the power detector’s output voltage and uses this
information to drive the GC1 pin directly. Voltage output
mode is enabled by setting the D[2:0] bits in the test reg-
ister to 100. In voltage mode, the PWRDET pin outputs a
scaled DC voltage proportional to the RF input power.
For the RF input range of -62dBm to -48dBm, the DC
output voltage ranges from 84mV to 420mV.
High-Side and Low-Side LO Injection
The MAX2160/EBG allow selection between high-side
and low-side LO injection through the HSLS bit in the
control register. High-side injection is the default setting
(HSLS = 1).
Q-Channel Shutdown
The Q channel low-IF output of the MAX2160/EBG can
be turned off with the QOFF bit in the XTAL divide reg-
ister for use with single low-IF input demodulators (use I
channel only). Turning off the Q channel reduces the
supply current by approximately 3mA.
START
WRITE DEVICE
ADDRESS
R/W
1100000 1
ACK
STOP
READ FROM STATUS
BYTE-1 REGISTER
ACK
READ FROM STATUS
BYTE-2 REGISTER
ACK/
NACK
Figure 3. Example: Receive Data from Read Registers
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

MAX2160ETL+T

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Buy MAX2160ETL+T
Manufacturer:
Maxim Integrated
Description:
Tuners ISDB-T Single-Seg Low-IF Tuner
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