MAX2160/MAX2160EBG
ISDB-T Single-Segment Low-IF Tuners
______________________________________________________________________________________ 19
IF Filter Tuning
The center frequency of the baseband bandpass filter
is tuned to 571kHz during production at the factory.
However, the factory-set trim may be bypassed and the
filter’s center frequency can be adjusted through the
FLTS and TUN[2:0] bits in the test register. Setting the
FLTS bit sets the filter’s center frequency to the factory-
set tuning, clearing the FLTS bit allows the filter’s center
frequency to be adjusted with the TUN[2:0] bits (see
Table 2).
Fixed IF Gain Step
To maintain the best possible sensitivity for both QPSK
and QAM signals, the MAX2160/EBG include a control
bit (MOD) to increase the gain of the baseband stage
by approximately 7dB. This gain step is intended to be
used when receiving QPSK signals. Set the MOD bit to
one in QPSK receive mode, set the MOD bit to zero in
QAM receive mode.
VCO Autoselect (VAS)
The MAX2160/EBG include four VCOs with each VCO
having eight sub-bands. The local oscillator frequency
can be manually selected by programming the
VCO[1:0] and VSB[2:0] bits in the VCO register. The
selected VCO and sub-band is reported in the STATUS
BYTE-2 register (see Table 11).
Alternatively, the MAX2160/EBG can be set to automati-
cally choose a VCO and VCO sub-band. Automatic
VCO selection is enabled by setting the VAS bit in the
PLL register, and is initiated once the N-divider LSB
register word is loaded. In the event that only the R-
divider register or N-divider MSB register word is
changed, the N-divider LSB word must also be loaded
(last) to initiate the VCO autoselect function. The VCO
and VCO sub-band that are programmed in the
VCO[1:0] and VSB[2:0] bits serve as the starting point
for the automatic VCO selection process.
During the selection process, the VASE bit in the
STATUS BYTE-2 register is cleared to indicate the auto-
matic selection function is active. Upon successful
completion, bits VASE and VASA are set and the VCO
and sub-band selected are reported in the STATUS
BYTE-2 register (see Table 11). If the search is unsuc-
cessful, VASA is cleared and VASE is set. This indi-
cates that searching has ended but no good VCO has
been found, and occurs when trying to tune to a fre-
quency outside the VCO’s specified frequency range.
Charge-Pump Select (CPS)
The MAX2160/EBG also allow for manual selection of the
charge-pump current (CPS = 0) or automatic selection
based on the final VTUNE ADC read value (CPS = 1).
When in manual mode, the charge-pump current is pro-
grammed by bits CP[1:0] with the 2-wire bus. When in
automatic selection mode, the CP[1:0] bits are automati-
cally set according to the ADC table (see Tables 12 and
13). The selected charge-pump current (manually or
automatically) is reported in the STATUS BYTE-1 register.
3-Bit ADC
The MAX2160/EBG have an internal 3-bit ADC connect-
ed to the VCO tune pin (VTUNE). This ADC can be
used for checking the lock status of the VCOs.
Table 13 summarizes the ADC trip points, associated
charge-pump settings (when CPS = 1), and the VCO
lock indication. The VCO autoselect routine will only
select a VCO in the “VAS locked” range. This allows
room for a VCO to drift over temperature and remain in
a valid “locked” range.
The ADC must first be enabled by setting the ADE bit in
the VCO register. The ADC reading is latched by a sub-
sequent programming of the ADC latch bit (ADL = 1).
The ADC value is reported in the STATUS BYTE-2
register (see Table 11).
Table 12. Charge-Pump Current Selection
VAS CPS VASA
CHARGE-PUMP VALUES
(CP[1:0])
0 0 X Values programmed with 2-wire bus
0 1 X Values selected by ADC read
1 0 X Values programmed with 2-wire bus
1 1 0 Values programmed with 2-wire bus
1 1 1 Values selected by ADC read
Table 13. ADC Trip Points, Associated
Charge-Pump Settings, and Lock Status
VTUNE (V
T
) ADC[2:0] CP[1:0] LOCK STATUS
V
T
< 0.41V 000 00 Out of Lock
0.41V < V
T
< 0.6V 001 00 Locked
0.6V < V
T
< 0.9V 010 00 VAS Locked
0.9V < V
T
< 1.3V 011 01 VAS Locked
1.3V < V
T
< 1.7V 100 10 VAS Locked
1.7V < V
T
< 1.9V 101 11 VAS Locked
1.9V < V
T
<
V
CC
- 0.41V
011 11 Locked
V
CC
- 0.41V < V
T
111 11 Out of Lock
MAX2160/MAX2160EBG
ISDB-T Single-Segment Low-IF Tuners
20 ______________________________________________________________________________________
Loop Time Constant Pin (LTC)
The LTC function sets the wait time for an ADC read
when in VCO autoselect mode. The time constant is set
by charging an external capacitor connected to the
LTC pin with a constant current source. The value of
the current source can be programmed to 1µA or 2µA
with the LTC bit in the VCO register (see Table 4).
The LTC time constant is determined by the following
equation:
Time constant = C
LTC
x 1.7 / I
LTC
where:
C
LTC
= capacitor connected from the
LTC pin to ground.
I
LTC
= 1µA (LTC = 0) or 2µA (LTC = 1).
Setting C
LTC
equal to 1000pF gives a time constant
of 1.7ms with I
LTC
set to 1µA and 0.85ms with I
LTC
set to 2µA.
ENTCXO
The MAX2160/EBG have both an integrated crystal
oscillator and a separate TCXO buffer amplfier. The
ENTCXO pin controls which reference source is used
(see Table 14).
XTALOUT Divider
A reference buffer/divider is provided for driving exter-
nal devices. The divider can be set for any division ratio
from 1 to 31 by programming the XD[4:0] bits in the
XTAL divide register (see Table 6). The buffer can be
disabled by setting XD[4:0] to all zeros.
Shutdown and Standby Modes
The MAX2160/EBG feature hardware- and software-
controlled shutdown mode as well as a software-con-
trolled standby mode. Driving the SHDN pin low with bit
EPD = 0 places the device in hardware shutdown
mode. In this mode, the entire device including the 2-
wire-compatible interface is turned off and the supply
current drops to less than 10µA. The hardware shut-
down pin overrides the software shutdown and standby
modes.
Setting the PWDN bit in the XTAL divide register
enables power-down mode. In this mode, all circuitry
except for the 2-wire-compatible bus is disabled, allow-
ing for programming of the MAX2160/EBGs’ registers
while in shutdown. Setting the STBY bit in the XTAL
divide register puts the device into standby mode, dur-
ing which only the 2-wire-compatible bus, the crystal
oscillator, the XTAL buffer, and the XTAL buffer-divider
are active.
In all cases, register settings loaded prior to entering
shutdown are saved upon transition back to active
mode. Default register values are loaded only when
V
CC
is applied from a no-V
CC
state. The various power-
down modes are summarized in Table 15. Supply cur-
rent fluctuations for nondefault register settings are
shown in Table 16.
Diagnostic Modes and Test Pin
The MAX2160/EBG have several diagnostic modes that
are controlled by the D[2:0] bits in the test register (see
Table 2). The local oscillator can be directed to the
TEST pin for LO measurements by setting the D[2:0] bits
to all ones. In this mode, the supply current will increase
by approximately 10mA. The TEST pin requires a 10k
pullup resistor to V
CC
for proper operation.
Table 14. Reference Source Selection
ENTCXO FUNCTION
V
CC
The TCXO input is enabled for use with an
external TCXO
GND
The XTAL input is enabled for use with an external
crystal
Table 15. Power-Down Modes
POWER-DOWN CONTROL CIRCUIT STATES
MODE
SHDN PIN
PWDN
BIT
STBY
BIT
SIGNAL
PATH
2-WIRE
INTERFACE
XTAL
DESCRIPTION
Normal V
CC
0 0 ON ON ON All circuits active
Shutdown GND X X OFF OFF OFF All circuits disabled
Power-Down V
CC
1 0 OFF ON OFF 2-wire interface is active
Standby V
CC
0 1 OFF ON ON
2-wire interface, XTAL, and XTAL
buffer/divider are active
MAX2160/MAX2160EBG
ISDB-T Single-Segment Low-IF Tuners
______________________________________________________________________________________ 21
Layout Considerations
The EV kit serves as a guide for PC board layout. Keep
RF signal lines as short as possible to minimize losses
and radiation. Use controlled impedance on all high-
frequency traces. For proper operation of the TQFN
package, the exposed paddle must be soldered evenly
to the board’s ground plane. Use abundant vias
beneath the exposed paddle for maximum heat dissi-
pation. Use abundant ground vias between RF traces
to minimize undesired coupling. Bypass each V
CC
pin
to ground with a 100pF capacitor placed as close to
the pin as possible.
In addition, the ground returns for the VCO, VTUNE,
and charge pump require special layout consideration.
The VCOBYP capacitor (C37) and the VCCVCO bypass
capacitor (C19) ground returns must be routed back to
the GNDVCO pin and then connected to the overall
ground plane at that point (GNDVCO). All loop filter
component grounds (C27–C30) and the VCCCP
bypass capacitor (C17) ground must all be routed
together back to the GNDCP pin. GNDTUNE must also
be routed back to the GNDCP pin along with all other
grounds from the PLL loop filter. The GNDCP pin must
then be connected to the overall ground plane. Figure
4 shows a schematic drawing of the required layout
connections. Refer to the MAX2160 evaluation kit for a
recommended board layout.
Table 16. Typical Supply Current Fluctuations for Nondefault Register Settings
MODE BIT CHANGE TYPICAL I
CC
TYPICAL I
CC
FROM
NOMINAL
Default register settings 46.5mA
QOFF = 1 (Q channel off) -3.3mA
BBL[1:0] = 00 (lower linearity) -2mA
BBL[1:0] = 01 (nominal linearity) -1mA
BBL[1:0] = 11 (high linearity) +1mA
MOD = 1 (7dB baseband gain step enabled) +0.3mA
EPD = 1 (power detector enabled) +1mA
EPB = 0 (charge-pump prebias disabled) +5.1mA
Receive
XD[4:0] = 00000 (XTALOUT buffer disabled) -40µA
Shutdown SHDN = GND 1µA
Standby STBY = 1 2.2mA
Power-Down PWDN = 1 13.5µA
VCOBYP
VCCVCO
GNDVCO
VTUNE
GNDTUNE
TEST
CPOUT
VCCCP
GNDCP
V
CC
V
CC
34 33 3238 37 36 3540 39
C17
C28
C27
C29 C30
R20
R21 R22
C19
C37
ROUTE GNDTUNE, C17, AND ALL
LOOP FILTER COMPONENT GROUNDS TO
GNDCP.
CONNECT GNDCP TO THE BOARD'S
GROUND PLANE.
ROUTE C19 AND C37 TO GNDVCO.
CONNECT GNDVCO TO THE BOARD'S
GROUND PLANE.
Figure 4. Ground Return Layout Connections for the VCO, Charge Pump, and VTUNE

MAX2160ETL+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Tuners ISDB-T Single-Seg Low-IF Tuner
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