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PTN3393BSY

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
PTN3393 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 10 June 2014 19 of 30
NXP Semiconductors
PTN3393
2-lane DisplayPort to VGA adapter IC
12.2 DisplayPort receiver main link
[1] Range is nominal 350 ppm. DisplayPort link RX does not require local crystal for link clock generation.
[2] Up to 0.5 % down spread is supported. Modulation frequency range of 30 kHz to 33 kHz must be supported.
[3] Informative; refer to Figure 7
for definition of differential voltage.
[4] t
RX_EYE_m-mJT_CHP
specifies the total allowable Deterministic Jitter (DJ).
[5] 1 t
RX_EYE_CONN
specifies the allowable Total Jitter (TJ).
[6] Common mode voltage is equal to V
bias_RX
voltage.
[7] Total drive current of the input bias circuit when it is shorted to its ground.
[8] Maximum skew limit between different RX lanes of a DisplayPort link.
[9] Maximum skew limit between D+ and D of the same lane.
[10] Minimum CDR tracking bandwidth at the receiver when the input is repetition of D10.2 symbols without scrambling.
Table 9. DisplayPort receiver main link characteristics
Symbol Parameter Conditions Min Typ Max Unit
UI unit interval for high bit rate
(2.7 Gbit/s per lane)
[1]
- 370 - ps
for low bit rate
(1.62 Gbit/s per lane)
[1]
- 617 - ps
f
DOWN_SPREAD
link clock down spreading
[2]
0.0- 0.5%
V
RX_DIFFp-p
differential input peak-to-peak
voltage
at RX package pins
for high bit rate
[3]
120 - - mV
for reduced bit rate
[3]
40 - - mV
t
RX_EYE_CONN
receiver eye time at RX-side
connector pins
for high bit rate
[4]
0.51 - - UI
for reduced bit rate
[4][5]
0.25 - - UI
t
RX_EYE_CHIP
receiver eye time at RX
package pins
for high bit rate
[4]
0.47 - - UI
for reduced bit rate
[4][5]
0.22 - - UI
t
RX_EYE_m-mJT_CHP
time between jitter median and
maximum median deviation
(package pins)
for high bit rate
[4]
- - 0.265 UI
for reduced bit rate
[4][5]
- - 0.39 UI
V
RX_DC_CM
RX DC common mode voltage
[6]
0- 2.0V
I
RX_SHORT
RX short-circuit current limit
[7]
--50mA
t
sk(dif)
differential skew time inter-pair; lane-to-lane skew
at RX package pins
[8]
- - 5200 ps
lane intra-pair skew at RX
package pins;
for high bit rate
[9]
- - 100 ps
for reduced bit rate
[9]
- - 300 ps
f
RX_TRACKING_BW
jitter tracking bandwidth
[10]
20 - - MHz
PTN3393 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 10 June 2014 20 of 30
NXP Semiconductors
PTN3393
2-lane DisplayPort to VGA adapter IC
12.3 DisplayPort receiver AUX CH
[1] Results in the bit rate of 1 Mbit/s including the overhead of Manchester II coding.
[2] Each pulse is a ‘0’ in Manchester II code.
[3] Period after the AUX CH STOP condition for which the bus is parked.
[4] Maximum allowable UI variation within a single transaction at connector pins of a transmitting device. Equal to 24 ns maximum. The
transmitting device is a source device for a request transaction and a sink device for a reply transaction.
[5] Maximum allowable UI variation within a single transaction at connector pins of a receiving device. Equal to 30 ns maximum. The
transmitting device is a source device for a request transaction and a sink device for a reply transaction.
[6] V
AUX_DIFFp-p
= 2 V
AUX+
V
AUX
.
[7] Common-mode voltage is equal to V
bias_TX
(or V
bias_RX
) voltage.
[8] Steady-state common-mode voltage shift between transmit and receive modes of operation.
[9] Total drive current of the transmitter when it is shorted to its ground.
[10] The AUX CH AC coupling capacitor placed both on the DisplayPort source and sink devices.
pre-emphasis = 20Log(V
DIFF_PRE
/V
DIFF
)
Fig 7. Definitions of pre-emphasis and differential voltage
Table 10. DisplayPort receiver AUX CH characteristics
Symbol Parameter Conditions Min Typ Max Unit
UI unit interval AUX
[1]
0.4 0.5 0.6 s
N
PRECHARGE_PULSES
number of precharge pulses
[2]
10 - 16
t
AUX_BUS_PARK
AUX CH bus park time
[3]
10 - - ns
t
jit(cc)
cycle-to-cycle jitter time transmitting device
[4]
- - 0.04 UI
receiving device
[5]
- - 0.05 UI
V
AUX_DIFFp-p
AUX differential peak-to-peak
voltage
transmitting device
[6]
0.39 - 1.38 V
receiving device
[6]
0.32 - 1.36 V
R
AUX_TERM(DC)
AUX CH termination DC resistance informative - 100 -
V
AUX_DC_CM
AUX DC common-mode voltage
[7]
0- 2.0V
V
AUX_TURN_CM
AUX turnaround common-mode
voltage
[8]
--0.4V
I
AUX_SHORT
AUX short-circuit current limit
[9]
--90mA
C
AUX
AUX AC coupling capacitor
[10]
75 - 200 nF
PTN3393 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 10 June 2014 21 of 30
NXP Semiconductors
PTN3393
2-lane DisplayPort to VGA adapter IC
12.4 HPD characteristics
12.5 DDC characteristics
[1] V
CC
is the pull-up voltage for DDC.
12.6 DAC
Table 11. HPD characteristics
Symbol Parameter Conditions Min Typ Max Unit
Output characteristics
V
OH
HIGH-level output voltage I
OH
=2mA 2--V
V
OL
LOW-level output voltage I
OL
= 2mA - - 0.8 V
I
OSH
HIGH-level short-circuit output
current
drive HIGH;
cell connected to ground
--129mA
I
OSL
LOW-level short-circuit output
current
drive LOW;
cell connected to V
DD
--126mA
Table 12. DDC characteristics
V
CC
= 4.5 V to 5.5 V.
[1]
Symbol Parameter Conditions Min Typ Max Unit
Input characteristics
V
IH
HIGH-level input voltage 2 - 5.5 V
V
IL
LOW-level input voltage 0.5 - +0.8 V
V
I(hys)
hysteresis of input voltage 0.1 V
DD
-- V
I
LI
input leakage current V
I
=5.5V - - 1 A
Output characteristics
I
OL
LOW-level output current V
OL
=0.4V 3.0 - - mA
I
O(sc)
short-circuit output current drive LOW;
cell connected to V
DD
--40.0mA
C
io
input/output capacitance V
I
= 3 V or 0 V; V
DD
=3.3V - 6 7 pF
V
I
= 3 V or 0 V; V
DD
=0V - 6 7 pF
Table 13. DAC characteristics
Symbol Parameter Conditions Min Typ Max Unit
N
res(DAC)
DAC resolution - - 8 bit
f
clk
clock frequency - - 240 MHz
I
o(DAC)
DAC output current variation DAC-to-DAC - - 4 %
INL integral non-linearity 1 0.5 +1 LSB
DNL differential non-linearity 1- +1LSB
V
o(DAC)
DAC output voltage 0 - 1.25 V
C
o(DAC)
DAC output capacitance - 3.5 - pF
ct(DAC)
DAC crosstalk between DAC outputs - 54 - dB
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PTN3393BSY

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Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized 2lane DisplayPort to VGA adapter testIC
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