PTN3393 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 10 June 2014 6 of 30
NXP Semiconductors
PTN3393
2-lane DisplayPort to VGA adapter IC
6.2 Pin description
Table 3. Pin description
Symbol Pin Type Description
Power
VDDD33_CORE 36 power Digital core 3.3 V supply voltage
VDDA33_AUX 1 power Analog AUX, bias and PLL 3.3 V supply
voltage
VDDA33_DP 14 power Analog 3.3 V supply for DisplayPort receiver
module
VDDD33_IO 21 power I/O 3.3 V supply voltage
VDDA33_DAC 27 power Analog 3.3 V supply for DAC
LDOCAP_AUX 2 power 1.8 V AUX supply decoupling
LDOCAP_DIG 35 power 1.8 V digital core supply decoupling
DisplayPort
ML0_P 6 self-biasing
differential input
DisplayPort main lane signal lane 0, positive
ML0_N 7 self-biasing
differential input
DisplayPort main lane signal lane 0,
negative
ML1_P 9 self-biasing
differential input
DisplayPort main lane signal lane 1, positive
ML1_N 10 self-biasing
differential input
DisplayPort main lane signal lane 1,
negative
AUX_P 3 self-biasing differential
input/output
DisplayPort auxiliary channel signal, positive
AUX_N 4 self-biasing differential
input/output
DisplayPort auxiliary channel signal,
negative
HPD 13 3.3 V TTL
single-ended output
Hot Plug Detect
RGB DAC outputs
BLU 26 analog output ‘blue’ current analog output
GRN 28 analog output ‘green’ current analog output
RED 31 analog output ‘red’ current analog output
RSET 30 analog input/output DAC full-scale current control resistor.
Pull down to ground by an external
1.2 k1 % resistor.
DDC
SCL 20 single-ended 5 V
open-drain DDC I/O
5 V sink-side DDC clock I/O. Pulled up by
external resistor to 5 V.
SDA 22 single-ended 5 V
open-drain DDC I/O
5 V sink-side DDC data I/O. Pulled up by
external resistor to 5 V.
Monitor-side sync
HSYNC 25 single-ended 3.3 V
TTL output
horizontal sync signal to monitor
VSYNC 24 single-ended 3.3 V
TTL output
vertical sync signal to monitor
