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ADGS1612BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
SPI Interface, 1 Ω R
ON
, ±5 V, 12 V, 5 V,
3.3 V, Mux Configurable, Quad SPST Switch
Data Sheet
ADGS1612
Rev. 0 Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
SPI interface with error detection
Includes CRC, invalid read/write address, and SCLK count
error detection
Supports burst mode and daisy-chain mode
Industry-standard SPI Mode 0 and SPI Mode 3 interface
compatible
Guaranteed break-before-make switching allowing external
wiring of switches to deliver multiplexer configurations
1 Ω typical on resistance at 25°C
0.23 Ω typical on resistance flatness at 25°C
V
SS
to V
DD
analog signal range
Fully specified at ±5 V, 12 V, 5 V, and 3.3 V
±3.3 V to ±8 V dual-supply operation
3.3 V to 16 V single-supply operation
1.8 V logic compatibility with 2.7 V ≤ V
L
≤ 3.3 V
4 mm × 4 mm, 24-lead LFCSP package
APPLICATIONS
Communication systems
Medical systems
Audio and video signal routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Relay replacements
FUNCTIONAL BLOCK DIAGRAM
SDO
D4S4
D3S3
D2S2
D1S1
SPI
INTERFACE
SCLK
SDI CS RESET/V
L
ADGS1612
16054-001
Figure 1.
GENERAL DESCRIPTION
The ADGS1612 contains four independent single-pole/single-
throw (SPST) switches. A serial peripheral interface (SPI) controls
the switches. The SPI interface has robust error detection features,
including cyclic redundancy check (CRC) error detection,
invalid read/write address detection, and serial clock (SCLK)
count error detection.
It is possible to daisy-chain multiple ADGS1612 devices together.
Daisy-chaining enables the configuration of multiple devices with a
minimal amount of digital lines. The ADGS1612 can also operate
in burst mode to decrease the time between SPI commands.
Each switch conducts equally well in both directions when on, and
each switch has an input signal range that extends to the supplies.
In the off condition, signal levels up to the supplies are blocked.
The ultralow on resistance (R
ON
) of these switches make them
ideal solutions for data acquisition and gain switching
applications where low R
ON
and low distortion are critical. The
R
ON
profile is very flat over the full analog input range, ensuring
excellent linearity and low distortion when switching audio
signals. The ADGS1612 exhibits break-before-make switching
action for use in multiplexer applications. Note that throughout
this data sheet, the multifunction pin,
RESET
/V
L
, is referred to
either by the entire pin name or by a single function of the pin,
for example, V
L
, when only that function is relevant.
PRODUCT HIGHLIGHTS
1. The SPI interface removes the need for parallel conversion
and logic traces and reduces general-purpose input/output
(GPIO) channel count.
2. Daisy-chain mode removes additional logic traces when
multiple devices are used.
3. CRC, invalid read/write address, and SCLK count error
detection ensure a robust digital interface.
4. CRC error detection capabilities allow the use of the
ADGS1612 in safety critical systems.
5. Guaranteed break-before-make switching allows the use of
the ADGS1612 in multiplexer configurations with external
wiring.
6. Minimum distortion.
ADGS1612 Data Sheet
Rev. 0 | Page 2 of 29
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±5 V Dual Supply ......................................................................... 3
12 V Single Supply ........................................................................ 5
5 V Single Supply .......................................................................... 7
3.3 V Single Supply ....................................................................... 9
Continuous Current per Channel, Sx or Dx ........................... 11
Timing Characteristics .............................................................. 11
Absolute Maximum Ratings .......................................................... 13
Thermal Resistance .................................................................... 13
ESD Caution ................................................................................ 13
Pin Configuration and Function Descriptions ........................... 14
Typical Performance Characteristics ........................................... 15
Test Circuits ..................................................................................... 19
Terminology .................................................................................... 21
Theory of Operation ...................................................................... 22
Address Mode ............................................................................. 22
Error Detection Features ........................................................... 22
Clearing the Error Flags Register ............................................. 23
Burst Mode .................................................................................. 23
Software Reset ............................................................................. 23
Daisy-Chain Mode ..................................................................... 23
Power-On Reset .......................................................................... 24
Applications Information .............................................................. 25
Break-Before-Make Switching .................................................. 25
Digital Input Buffers .................................................................. 25
Power Supply Rails ..................................................................... 25
Register Summary .......................................................................... 26
Register Details ............................................................................... 27
Switch Data Register .................................................................. 27
Error Configuration Register .................................................... 27
Error Flags Register .................................................................... 28
Burst Enable Register ................................................................. 28
Software Reset Register ............................................................. 28
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
1/2018—Revision 0: Initial Version
Data Sheet ADGS1612
Rev. 0 | Page 3 of 29
SPECIFICATIONS
±5 V DUAL SUPPLY
Positive supply (V
DD
) = 5 V ± 10%, negative supply (V
SS
) = −5 V ± 10%, digital supply (V
L
) = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V
DD
to V
SS
V
On Resistance, R
ON
1 Ω typ
V
S
= ±4.5 V, I
S
= −10 mA;
see Figure 29
1.2 1.4 1.6 Ω max V
DD
= +4.5 V, V
SS
= −4.5 V
On Resistance Match Between
Channels, ∆R
ON
0.04 Ω typ V
S
= ±4.5 V, I
S
= −10 mA
0.08 0.09 0.1 Ω max
On Resistance Flatness, R
FLAT (ON)
0.23 Ω typ V
S
= ±4.5 V, I
S
= −10 mA
0.28 0.32 0.37 Ω max
LEAKAGE CURRENTS V
DD
= +5.5 V, V
SS
= −5.5 V
Source Off Leakage, I
S
(Off) ±0.1 nA typ
V
S
= ±4.5 V, V
D
= ∓4.5 V; see Figure 32
±0.3 ±1.0 ±6.0 nA max
Drain Off Leakage, I
D
(Off) ±0.1 nA typ
V
S
= ±4.5 V, V
D
= ∓4.5 V; see Figure 32
±0.3 ±1.0 ±6.0 nA max
Channel On Leakage, I
D
(On), I
S
(On) ±0.2 nA typ V
S
= V
D
= ±4.5 V; see Figure 28
±0.4 ±1.5 ±10.0 nA max
DIGITAL OUTPUT
Output Voltage
Low, V
OL
0.4 V max I
SINK
= 5 mA
0.2 V max I
SINK
= 1 mA
Output Current, Low (I
OL
) or High (I
OH
) 0.001 μA typ V
OUT
= V
GND
or V
L
±0.1 μA max
Digital Output Capacitance, C
OUT
4 pF typ
DIGITAL INPUTS
Input Voltage
High, V
INH
2 V min 3.3 V < V
L
≤ 5.5 V
1.35 V min 2.7 V ≤ V
L
≤ 3.3 V
Low, V
INL
0.8 V max 3.3 V < V
L
≤ 5.5 V
0.8 V max 2.7 V ≤ V
L
≤ 3.3 V
Input Current, Low (I
INL
) or High (I
INH
) 0.001 μA typ V
IN
= V
GND
or V
L
±0.1 μA max
Digital Input Capacitance, C
IN
4 pF typ
DYNAMIC CHARACTERISTICS
On Time, t
ON
385 ns typ R
L
= 300 Ω, C
L
= 35 pF
480 485 485 ns max V
S
= 2.5 V; see Figure 36
Off Time, t
OFF
250 ns typ R
L
= 300 Ω, C
L
= 35 pF
305 335 360 ns max V
S
= 2.5 V; see Figure 36
Break-Before-Make Time Delay, t
D
175 ns typ R
L
= 300 Ω, C
L
= 35 pF
115 ns min V
S1
= V
S2
= 2.5 V, see Figure 35
Charge Injection, Q
INJ
120 pC typ
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF; see
Figure 37
Off Isolation −65 dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 100 kHz; see
Figure 31
Channel to Channel Crosstalk −93 dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see
Figure 30
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ADGS1612BCPZ

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Analog Switch ICs SPI Low Ron 4xSPST
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