Data Sheet ADGS1612
Rev. 0 | Page 25 of 29
APPLICATIONS INFORMATION
BREAK-BEFORE-MAKE SWITCHING
The ADGS1612 exhibits break-before-make switching action,
which allows the use of the device in multiplexer applications. A
multiplexer can be achieved by externally hardwiring the device
in the mux configuration that is required, as shown in Figure 45.
4 × SPST
S1
S4
S2
S3
D
1
4:1 MUX
SCLK SDI
CS
RESET/V
L
SPI
INTERFACE
16054-045
1
ALL Dx PINS ARE CONNECTED AS ONE DRAIN.
Figure 45. SPI Controlled Switch Configured as a 4:1 Mux
DIGITAL INPUT BUFFERS
There are input buffers present on the digital inputs pins,
CS
,
SCLK, and SDI. These buffers are active at all times. Therefore,
there is current draw from the V
L
supply if SCLK or SDI is
toggling, regardless of whether
CS
is active. For typical values of
this current draw, refer to the Specifications section and Figure 26.
POWER SUPPLY RAILS
To guarantee correct operation of the ADGS1612, 0.1 μF
decoupling capacitors are required.
The ADGS1612 can operate with bipolar supplies between
±3.3 V and ±8 V. The supplies on V
DD
and V
SS
do not have to be
symmetrical; however, the V
DD
to V
SS
range must not exceed
16 V. The ADGS1612 can also operate with single supplies
between 3.3 V and 16 V with V
SS
connected to GND.
The voltage range that can be supplied to V
L
is from 2.7 V to 5.5 V.
The device is fully specified at ±5 V, 12 V, 5 V, and 3.3 V analog
supply voltage ranges.
ADGS1612 Data Sheet
Rev. 0 | Page 26 of 29
REGISTER SUMMARY
Table 11. Register Summary
Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default RW
0x01 SW_DATA [7:0] RESERVED SW4_EN SW3_EN SW2_EN SW1_EN 0x00 R/W
0x02 ERR_CONFIG [7:0] RESERVED RW_ERR_EN SCLK_ERR_EN CRC_ERR_EN 0x06 R/W
0x03 ERR_FLAGS [7:0] RESERVED RW_ERR_FLAG SCLK_ERR_FLAG CRC_ERR_FLAG 0x00 R
0x05 BURST_EN [7:0] RESERVED BURST_MODE_EN 0x00 R/W
0x0B SOFT_RESETB [7:0] SOFT_RESETB 0x00 R/W
Data Sheet ADGS1612
Rev. 0 | Page 27 of 29
REGISTER DETAILS
SWITCH DATA REGISTER
Address: 0x01, Reset: 0x00, Name: SW_DATA
The switch data register controls the status of the four switches of the ADGS1612.
Table 12. Bit Descriptions for SW_DATA
Bits Bit Name Settings Description Default Access
[7:4] RESERVED These bits are reserved; set these bits to 0. 0x0 R
3 SW4_EN Enable bit for SW4. 0x0 R/W
0 SW4 open.
1 SW4 closed.
2 SW3_EN Enable bit for SW3. 0x0 R/W
0 SW3 open.
1 SW3 closed.
1 SW2_EN Enable bit for SW2. 0x0 R/W
0 SW2 open.
1 SW2 closed.
0 SW1_EN Enable bit for SW1. 0x0 R/W
0 SW1 open.
1 SW1 closed.
ERROR CONFIGURATION REGISTER
Address: 0x02, Reset: 0x06, Name: ERR_CONFIG
The error configuration register allows the user to enable or disable the relevant error features as required.
Table 13. Bit Descriptions for ERR_CONFIG
Bits Bit Name Settings Description Default Access
[7:3] RESERVED These bits are reserved; set these bits to 0. 0x0 R
2 RW_ERR_EN Enable bit for detecting an invalid read/write address. 0x1 R/W
0 Disabled.
1 Enabled.
1 SCLK_ERR_EN
Enable bit for detecting the correct number of SCLK cycles in an SPI frame. When
CRC is disabled and burst mode is disabled, 16 SCLK cycles are expected. When
CRC is enabled and burst mode is disabled, 24 SCLK cycles are expected. A multiple
of 16 SCLK cycles is expected when CRC is disabled and burst mode is enabled. A
multiple of 24 SCLK cycles is expected when CRC is enabled and burst mode is
enabled.
0x1 R/W
0 Disabled.
1 Enabled.
0 CRC_ERR_EN Enable bit for CRC error detection. SPI frames must be 24 bits wide when enabled. 0x0 R/W
0 Disabled.
1 Enabled.

ADGS1612BCPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Switch ICs SPI Low Ron 4xSPST
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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