ADGS1612 Data Sheet
Rev. 0 | Page 22 of 29
THEORY OF OPERATION
The ADGS1612 is a set of serially controlled, quad SPST switches
with error detection features. SPI Mode 0 and SPI Mode 3 can
be used with the device, and it operates with SCLK frequencies
of up to 50 MHz. The default mode for the ADGS1612 is address
mode, in which the registers of the device are accessed by a 16-bit
SPI command bounded by
CS
. The SPI command becomes 24-bit
if the user enables CRC error detection. Other error detection
features include SCLK count error and invalid read/write error. If
any of these SPI interface errors occur, they are detectable by
reading the error flags register. The ADGS1612 can also operate
in two other modes, namely burst mode and daisy-chain mode.
The interface pins of the ADGS1612 are
CS
, SCLK, SDI, and
SDO. Hold
CS
low when using the SPI interface. Data is captured
on the SDI pin on the rising edge of SCLK, and data is propagated
out on the SDO pin on the falling edge of SCLK. SDO has an
open-drain output; thus, connect a pull-up resistor to this
output. When not pulled low by the ADGS1612, SDO is in a
high impedance state.
ADDRESS MODE
Address mode is the default mode for the ADGS1612 on
power-up. A single SPI frame in address mode is bounded by a
CS
falling edge and the succeeding
CS
rising edge. The SPI frame
is composed of 16 SCLK cycles. The timing diagram for address
mode is shown in Figure 39. The first SDI bit indicates whether
the SPI command is a read or write command. When the first
bit is set to 0, a write command is issued, and if the first bit is set
to 1, a read command is issued. The next seven bits determine the
target register address. The remaining eight bits provide the data
to the addressed register. The last eight bits are ignored during a
read command, because during these clock cycles, SDO
propagates out the data contained in the addressed register.
The target register address of an SPI command is determined on
the eighth SCLK rising edge. Data from this register propagates out
on SDO from the ninth to the 16
th
SCLK falling edge during SPI
reads. A register write occurs on the 16
th
SCLK rising edge
during SPI writes.
During any SPI command, SDO sends out eight alignment bits
on the first eight SCLK falling edges. The alignment bits observed
at SDO are 0x25.
ERROR DETECTION FEATURES
Protocol and communication errors on the SPI interface are
detectable. There are three detectable errors: incorrect SCLK error
detection, invalid read and write address error detection, and
CRC error detection. Each of these errors has a corresponding
enable bit in the error configuration register. In addition, there
is an error flag bit for each of these errors in the error flags
register.
Cyclic Redundancy Check (CRC) Error Detection
The CRC error detection feature extends a valid SPI frame by
eight SCLK cycles. These eight extra cycles are needed to send the
CRC byte for that SPI frame. The CRC byte is calculated by the SPI
block using the 16-bit payload: the R/
W
bit, Address Bits[6:0], and
Data Bits[7:0]. The CRC polynomial used in the SPI block is
x
8
+ x
2
+ x
1
+ 1 with a seed value of 0. For a timing diagram with
CRC enabled, see Figure 40. Register writes occur at the 24
th
SCLK
rising edge with CRC error checking enabled.
During an SPI write, the microcontroller/CPU provides the
CRC byte through SDI. The SPI block checks the CRC byte just
before the 24
th
SCLK rising edge. On this same edge, the register
write is prevented if an incorrect CRC byte is received by the
SPI interface. The CRC error flag is asserted in the error flags
register in the case of the incorrect CRC byte being detected.
During an SPI read, the CRC byte is provided to the microcon-
troller through SDO.
The CRC error detection feature is disabled by default and can
be configured by the user through the error configuration register.
0 0 1 0 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0SDO
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 10111213141516
SDI
SCLK
CS
16054-039
Figure 39. Address Mode Timing Diagram
0 0 1 D7 D6 D0 C7 C6 C5 C4 C3 C2 C1 C0SDO
R/W A6 A0 D7 D6 D0 C7 C6 C5 C4 C3 C2 C1 C0
1 2 8 9 10 16 17 18 19 20 21 22 23 24
SDI
SCLK
CS
16054-040
Figure 40. Timing Diagram with CRC Enabled
