Data Sheet ADGS1612
Rev. 0 | Page 11 of 29
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5. Four Channels On
Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR Dx
V
DD
= +5 V, V
SS
= −5 V (θ
JA
= 60°C/W) 315 194 106 mA max
V
DD
= 12 V, V
SS
= 0 V (θ
JA
= 60°C/W) 330 200 108 mA max
V
DD
= 5 V, V
SS
= 0 V (θ
JA
= 60°C/W) 249 161 96 mA max
V
DD
= 3.3 V, V
SS
= 0 V (θ
JA
= 60°C/W) 203 137 87 mA max
Table 6. One Channel On
Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR Dx
V
DD
= +5 V, V
SS
= −5 V (θ
JA
= 60°C/W) 566 292 126 mA max
V
DD
= 12 V, V
SS
= 0 V (θ
JA
= 60°C/W) 591 301 127 mA max
V
DD
= 5 V, V
SS
= 0 V (θ
JA
= 60°C/W) 450 251 120 mA max
V
DD
= 3.3 V, V
SS
= 0 V (θ
JA
= 60°C/W) 366 218 113 mA max
TIMING CHARACTERISTICS
V
L
= 2.7 V to 5.5 V; GND = 0 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 7.
Parameter Limit at T
MIN
, T
MAX
Unit Description
t
1
20 ns min SCLK period
t
2
8 ns min SCLK high pulse width
t
3
8 ns min SCLK low pulse width
t
4
10 ns min
CS
falling edge to SCLK rising edge
t
5
6 ns min Data setup time
t
6
8 ns min Data hold time
t
7
10 ns min
SCLK active edge to CS
rising edge
t
8
20 ns max
CS
falling edge to SDO data available
t
9
1
20 ns max SCLK falling edge to SDO data available
t
10
20 ns max
CS
rising edge to SDO returns to high impedance
t
11
20 ns min
CS
high time between SPI commands
t
12
8 ns min
CS
falling edge to SCLK becomes stable
t
13
8 ns min
CS
rising edge to SCLK becomes stable
1
Measured with the 1 kΩ pull-up resistor to V
L
and 20 pF load. The t
9
parameter determines the maximum SCLK frequency when SDO is used.
