ADGS1612 Data Sheet
Rev. 0 | Page 28 of 29
ERROR FLAGS REGISTER
Address: 0x03, Reset: 0x00, Name: ERR_FLAGS
The error flags register allows the user to determine if an error occurred. To clear the error flags register, the special 16-bit SPI command,
0x6CA9, must be written to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, then
the user must include the correct CRC byte during the SPI write for the clear error flags register command to complete.
Table 14. Bit Descriptions for ERR_FLAGS
Bits Bit Name Settings Description Default Access
[7:3] RESERVED These bits are reserved and are set to 0. 0x0 R
2 RW_ERR_FLAG
Error flag for invalid read/write address. The error flag asserts during an SPI read
if the target address does not exist. The error flag also asserts when the target
address of an SPI write does not exist or is read only.
0x0 R
0 No error.
1 Error.
1 SCLK_ERR_FLAG Error flag for the detection of the correct number of SCLK cycles in an SPI frame. 0x0 R
0 No error.
1 Error.
0 CRC_ERR_FLAG Error flag that determines if a CRC error occurs during a register write. 0x0 R
0 No error.
1 Error.
BURST ENABLE REGISTER
Address: 0x05, Reset: 0x00, Name: BURST_EN
The burst enable register allows the user to enable or disable burst mode. When enabled, the user can send multiple consecutive SPI
commands without deasserting
CS
.
Table 15. Bit Descriptions for BURST_EN
Bits Bit Name Settings Description Default Access
[7:1] RESERVED These bits are reserved; set these bits to 0. 0x0 R
0 BURST_MODE_EN Burst mode enable bit. 0x0 R/W
0 Disabled.
1 Enabled.
SOFTWARE RESET REGISTER
Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB
This software reset register is used to perform a software reset. Consecutively write 0xA3 and 0x05 to this register, and the device registers
reset to their default states.
Table 16. Bit Descriptions for SOFT_RESETB
Bits Bit Name Settings Description Default Access
[7:0] SOFT_RESETB
To perform a software reset, consecutively write 0xA3 followed by 0x05 to this
register.
0x0 R/W
