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LTC4269CDKD-1#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
LTC4269-1
19
42691fc
reliably not only when an initially charged cable connects
and dissipates the energy through the PD front end, but
also when the electrical power system grounds are subject
to very high energy events (e.g. lightning strikes).
In these high energy events, adding 10 series resistance
into the V
PORTP
pin greatly improves the robustness of
the LTC4269-1 based PD. (See Figure 7) The TVS limits
the voltage across the port while the 10 and 0.1µF ca-
pacitance reduces the edge rate the LT4269-1 encounters
across its pin. The added10 series resistance does not
operationally affect the LTC4269-1 PD interface nor does
it affect its compliance with the IEEE802.3 standard.
Transient Voltage Suppressor
The LTC4269-1 specifi es an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events.
However, the pins that interface to the outside world can rou-
tinely see excessive peak voltages. To protect the LTC4269-
1, install a transient voltage suppressor (D3) between the
input diode bridge and the LTC4269-1 as shown in Figure 7.
A SMAJ58A is recommended for typical PD applications.
However, a SMBJ58A may be preferred in applications
where the PD front end must absorb higher energy dis-
charge events.
Classifi cation Resistor (R
CLASS
)
The R
CLASS
resistor sets the classifi cation load current, cor-
responding to the PD power classifi cation. Select the value
of R
CLASS
from Table 2 and connect the resistor between
the R
CLASS
and V
PORTN
pins as shown in Figure 4, or fl oat
the R
CLASS
pin if the classifi cation load current is not re-
quired. The resistor tolerance must be 1% or better to avoid
degrading the overall accuracy of the classifi cation circuit.
Load Capacitor
The IEEE 802.3af/at specifi cation requires that the PD
maintains a minimum load capacitance of 5F and does
not specify a maximum load capacitor. However, if the
load capacitor is too large, there may be a problem with
inadvertent power shutdown by the PSE.
This occurs when the PSE voltage drops quickly. The input
diode bridge reverses bias, and the PD load momentarily
powers off the load capacitor. If the PD does not draw
power within the PSE’s 300ms disconnection delay, the
PSE may remove power from the PD. Thus, it is necessary
to evaluate the load current and capacitance to ensure that
an inadvertent shutdown cannot occur.
The load capacitor can store signifi cant energy when fully
charged. The PD design must ensure that this energy is not
inadvertently dissipated in the LTC4269-1. For example,
if the V
PORTP
pin shorts to V
PORTN
while the capacitor
is charged, current will fl ow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4269-1.
T2P Interface
When a 2-event classifi cation sequence successfully
completes, the LTC4269-1 recognizes this sequence,
and provides an indicator bit, declaring the presence of
a Type 2 PSE. The open-drain output provides the option
to use this signal to communicate to the LTC4269-1 load,
or to leave the pin unconnected.
Figure 8 shows two interface options using the T2P pin
and the opto-isolator. The T2P pin is active low and con-
nects to an opto-isolator to communicate across the DC/
DC converter isolation barrier. The pull-up resistor R
P
is
sized according to the requirements of the opto-isolator
APPLICATIONS INFORMATION
42691 F08
OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT
–54V
TO
PSE
R
P
TO PD LOAD
V
PORTP
LTC4269-1
V
PORTN
T2P
V
+
OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT
–54V
TO
PSE
R
P
TO PD LOAD
V
PORTP
LTC4269-1
V
PORTN
T2P
V
+
Figure 8. T2P Interface Examples
LTC4269-1
20
42691fc
operating current, the pull-down capability of the T2P pin,
and the choice of V
+
. V
+
for example can come from the
PoE supply rail (which the LTC4269-1 V
PORTP
is tied to),
or from the voltage source that supplies power to the DC/
DC converter. Option 1 has the advantage of not drawing
power unless T2P is declared active.
Shutdown Interface
To corrupt the signature resistance, the SHDN pin can be
driven high with respect to V
PORTN
. If unused, connect
SHDN directly to V
PORTN
.
Auxiliary Power Source
In some applications, it is desirable to power the PD from
an auxiliary power source such as a wall adapter.
Auxiliary power can be injected into an LTC4269-1-based
PD at the input of the LTC4269-1 V
PORTN
, at V
NEG
, or even
the power supply output. In addition, some PD application
may desire auxiliary supply dominance or may be con-
fi gured for PoE dominance. Furthermore, PD applications
may also opt for a seamless transition — that is, without
power disruption — between PoE and auxiliary power.
The most common auxiliary power option injects power at
V
NEG
. Figure 9 presents an example of this application. In
this example, the auxiliary port injects 48V onto the line via
diode D1. The components surrounding the SHDN pin are
selected so that the LTC4269-1 does not disconnect power
to the output until the auxiliary supply exceeds 36V.
This confi guration is an auxiliary-dominant confi guration.
That is, the auxiliary power source supplies the power even
if PoE power is already present. This confi guration also
provides a seamless transition from PoE to auxiliary power
when auxiliary power is applied, however, the removal of
auxiliary power to PoE power is not seamless.
Contact Linear Technology applications support for detail
information on implementing a custom auxiliary power
supply.
IEEE 802.3at SYSTEM POWER-UP REQUIREMENT
Under the IEEE 802.3at standard, a PD must operate
under 13.0W as a Type 1 PD until it recognizes a Type 2
PSE. Initializing PD operation in 13.0W mode eliminates
interoperability issue in case a Type 2 PD connects to a
Type 1 PSE. Once the PD recognizes a Type 2 PSE, the
IEEE 802.3at standard requires the PD to wait 80ms in
13.0W operation before 25.5W operation can commence.
MAINTAIN POWER SIGNATURE
In an IEEE 802.3af/at system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically draw
at least 10mA and also have an AC impedance less than
26.25k in parallel with 0.05F. If one of these conditions
is not met, the PSE may disconnect power to the PD.
APPLICATIONS INFORMATION
Figure 9. Auxiliary Power Dominant PD Interface Example
T1
42691 F09
TVS
TO PHY
36V
100k
10k
10k
D1
BR1
+
–
BR2
+
–
0.1µF
100V
C1
V
PORTP
LTC4269-1
V
PORTN
SHDN
V
NEG
GND
+
–
ISOLATED
WALL
TRANSFORMER
RX
–
6
RX
+
3
TX
–
2
TX
+
RJ45
1
7
8
5
4
SPARE
–
SPARE
+
LTC4269-1
21
42691fc
SWITCHING REGULATOR OVERVIEW
The LTC4269-1 includes a current mode converter designed
specifi cally for use in an isolated fl yback topology employing
synchronous rectifi cation. The LTC4269-1 operation is
similar to traditional current mode switchers. The major
difference is that output voltage feedback is derived via
sensing the output voltage through the transformer. This
precludes the need of an opto-isolator in isolated designs,
thus greatly improving dynamic response and reliability.
The LTC4269-1 has a unique feedback amplifi er that
samples a transformer winding voltage during the fl yback
period and uses that voltage to control output voltage.
The internal blocks are similar to many current mode
controllers. The differences lie in the feedback amplifi er and
load compensation circuitry. The logic block also contains
circuitry to control the special dynamic requirements of
fl yback control. For more information on the basics of
current mode switcher/controllers and isolated fl yback
converters see Application Note 19.
Feedback Amplifi er—Pseudo DC Theory
For the following discussion, refer to the simplifi ed
Switching Regulator Feedback Amplifi er diagram (Figure
10A). When the primary-side MOSFET switch MP turns off,
its drain voltage rises above the V
PORTP
rail. Flyback occurs
when the primary MOSFET is off and the synchronous
secondary MOSFET is on. During fl yback the voltage on
nondriven transformer pins is determined by the secondary
voltage. The amplitude of this fl yback pulse, as seen on
the third winding, is given as:
V
FLBK
=
V
OUT
+I
SEC
•ESR+R
DS(ON)
()
N
SF
R
DS(ON)
= on-resistance of the synchronous MOSFET MS
I
SEC
= transformer secondary current
ESR = impedance of secondary circuit capacitor, winding
and traces
N
SF
= transformer effective secondary-to-fl yback winding
turns ratio (i.e., N
S
/N
FLBK
)
The fl yback voltage is scaled by an external resistive
divider R1/R2 and presented at the FB pin. The feedback
amplifi er compares the voltage to the internal bandgap
reference. The feedback amp is actually a transconductance
APPLICATIONS INFORMATION
amplifi er whose output is connected to V
CMP
only during
a period in the fl yback time. An external capacitor on
the V
CMP
pin integrates the net feedback amp current to
provide the control voltage to set the current mode trip
point. The regulation voltage at the FB pin is nearly equal
to the bandgap reference V
FB
because of the high gain in
the overall loop. The relationship between V
FLBK
and V
FB
is expressed as:
V
FLBK
=
R1+R2
R2
•V
FB
Combining this with the previous V
FLBK
expression yields
an expression for V
OUT
in terms of the internal reference,
programming resistors and secondary resistances:
V
OUT
=
R1+R2
R2
•V
FB
•N
SF
⎛
⎝
⎜
⎞
⎠
⎟
−I
SEC
•ESR+R
DS(ON)
()
The effect of nonzero secondary output impedance is
discussed in further detail (see Load Compensation
Theory). The practical aspects of applying this equation for
V
OUT
are found in subsequent sections of the Applications
Information.
Feedback Amplifi er Dynamic Theory
So far, this has been a pseudo-DC treatment of fl yback
feedback amplifi er operation. But the fl yback signal is a
pulse, not a DC level. Provision is made to turn on the
fl yback amplifi er only when the fl yback pulse is present,
using the enable signal as shown in the timing diagram
(Figure 10b).
Minimum Output Switch On Time (t
ON(MIN)
)
The LTC4269-1 affects output voltage regulation via
fl yback pulse action. If the output switch is not turned on,
there is no fl yback pulse and output voltage information
is not available. This causes irregular loop response and
start-up/latchup problems. The solution is to require the
primary switch to be on for an absolute minimum time per
each oscillator cycle. To accomplish this the current limit
feedback is blanked each cycle for t
ON(MIN)
. If the output load
is less than that developed under these conditions, forced
continuous operation normally occurs. See subsequent
discussions in the Applications Information section for
further details.
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LTC4269CDKD-1#PBF

Mfr. #:
Buy LTC4269CDKD-1#PBF
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN IEEE 802.3at High Power PD Controller with Flyback Switcher
Lifecycle:
New from this manufacturer.
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