LTC4269-1
28
42691fc
APPLICATIONS INFORMATION
Selecting the Load Compensation Resistor
The expression for R
CMP
was derived in the Operation
section as:
R
CMP
=K1
R
SENSE
•1DC
()
ESR+R
DS(ON)
•R1•N
SF
Continuing the example:
K1=
V
OUT
V
IN
•Eff
=
5
48 90%
= 0.116
DC=
1
1+
N•V
IN(NOM)
V
OUT
=
1
1+
1
8
48
5
= 45.5%
If ESR+R
DS(ON)
= 8mΩ
R
CMP
= 0.116
33mΩ •10.455
()
8mΩ
37.4kΩ
1
3
= 3.25k
This value for R
CMP
is a good starting point, but empirical
methods are required for producing the best results.
This is because several of the required input variables
are diffi cult to estimate precisely. For instance, the ESR
term above includes that of the transformer secondary,
but its effective ESR value depends on high frequency
behavior, not simply DC winding resistance. Similarly, K1
appears as a simple ratio of V
IN
to V
OUT
times effi ciency,
but theoretically estimating effi ciency is not a simple
calculation.
The suggested empirical method is as follows:
1. Build a prototype of the desired supply including the
actual secondary components.
2. Temporarily ground the C
CMP
pin to disable the load
compensation function. Measure output voltage while
sweeping output current over the expected range.
Approximate the voltage variation as a straight line.
ΔV
OUT
/ΔI
OUT
= R
S(OUT)
.
3. Calculate a value for the K1 constant based on V
IN
, V
OUT
and the measured effi ciency.
4. Compute:
R
CMP
=K1
R
SENSE
R
S(OUT)
•R1•N
SF
5. Verify this result by connecting a resistor of this value
from the R
CMP
pin to ground.
6. Disconnect the ground short to C
CMP
and connect a 0.1µF
lter capacitor to ground. Measure the output imped-
ance R
S(OUT)
= ΔV
OUT
/ΔI
OUT
with the new compensation
in place. R
S(OUT)
should have decreased signifi cantly.
Fine tuning is accomplished experimentally by slightly
altering R
CMP
. A revised estimate for R
CMP
is:
R
CMP
=R
CMP
•1+
R
S(OUT)CMP
R
S(OUT)
where Rʹ
CMP
is the new value for the load compensation
resistor. R
S(OUT)CMP
is the output impedance with R
CMP
in place and R
S(OUT)
is the output impedance with no
load compensation (from step 2).
Setting Frequency
The switching frequency of the LTC4269-1 is set by an
external capacitor connected between the OSC pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz. Figure 12 shows the nominal relationship between
external capacitance and switching frequency. Place the
capacitor as close as possible to the IC and minimize OSC
C
OSC
(pF)
30
50
f
OSC
(kHz)
100
200
300
100 200
42691 F12
Figure 12. f
OSC
vs OSC Capacitor Values
LTC4269-1
29
42691fc
APPLICATIONS INFORMATION
trace length and area to minimize stray capacitance and
potential noise pick-up.
You can synchronize the oscillator frequency to an
external frequency. This is done with a signal on the SYNC
pin. Set the LTC4269-1 frequency 10% slower than the
desired external frequency using the OSC pin capacitor,
then use a pulse on the SYNC pin of amplitude greater
than 2V and with the desired frequency. The rising edge
of the SYNC signal initiates an OSC capacitor discharge
forcing primary MOSFET off (PG voltage goes low). If
the oscillator frequency is much different from the sync
frequency, problems may occur with slope compensation
and system stability. Also, keep the sync pulse width
greater than 500ns.
Selecting Timing Resistors
There are three internal “one-shot” times that are
programmed by external application resistors: minimum
on-time, enable delay time and primary MOSFET turn-on
delay. These are all part of the isolated fl yback control
technique, and their functions are previously outlined in
the Theory of Operation section. The following information
should help in selecting and/or optimizing these timing
values.
Minimum Output Switch On-Time (t
ON(MIN)
)
Minimum on-time is the programmable period during which
current limit is blanked (ignored) after the turn-on of the
primary-side switch. This improves regulator performance
by eliminating false tripping on the leading edge spike in
the switch, especially at light loads. This spike is due to
both the gate/source charging current and the discharge
of drain capacitance. The isolated fl yback sensing requires
a pulse to sense the output. Minimum on-time ensures
that the output switch is always on a minimum time and
that there is always a signal to close the loop.
The LTC4269-1 does not employ cycle skipping at light
loads. Therefore, minimum on-time along with synchro-
nous rectifi cation sets the switch over to forced continuous
mode operation.
The t
ON(MIN)
resistor is set with the following equation
R
tON(MIN)
kΩ
()
=
t
ON(MIN)
ns
()
104
1.063
Keep R
tON(MIN)
greater than 70k. A good starting value
is 160k.
Enable Delay Time (ENDLY)
Enable delay time provides a programmable delay between
turn-off of the primary gate drive node and the subsequent
enabling of the feedback amplifi er. As discussed earlier,
this delay allows the feedback amplifi er to ignore the
leakage inductance voltage spike on the primary side.
The worst-case leakage spike pulse width is at maximum
load conditions. So, set the enable delay time at these
conditions.
While the typical applications for this part use forced
continuous operation, it is conceivable that a secondary-
side controller might cause discontinuous operation at
light loads. Under such conditions, the amount of energy
stored in the transformer is small. The fl yback waveform
becomes “lazy” and some time elapses before it indicates
the actual secondary output voltage. The enable delay time
should be made long enough to ignore the “irrelevant”
portion of the fl yback waveform at light loads.
Even though the LTC4269-1 has a robust gate drive, the gate
transition time slows with very large MOSFETs. Increase
delay time as required when using such MOSFETs.
The enable delay resistor is set with the following
equation:
R
ENDLY
kΩ
()
=
t
ENDLY
ns
()
30
2.616
Keep R
ENDLY
greater than 40k. A good starting point is
56k.
LTC4269-1
30
42691fc
Primary Gate Delay Time (PGDLY)
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of the
primary-side MOSFET. Correct setting eliminates overlap
between the primary-side switch and secondary-side syn-
chronous switch(es) and the subsequent current spike in
the transformer. This spike will cause additional component
stress and a loss in regulator effi ciency.
The primary gate delay resistor is set with the following
equation:
R
PGDLY
kΩ
()
=
t
PGDLY
ns
()
+47
9.01
A good starting point is 15k.
Soft-Start Function
The LTC4269-1 contains an optional soft-start function that
is enabled by connecting an external capacitor between the
SFST pin and ground. Internal circuitry prevents the control
voltage at the V
CMP
pin from exceeding that on the SFST
pin. There is an initial pull-up circuit to quickly bring the
SFST voltage to approximately 0.8V. From there it charges
to approximately 2.8V with a 20µA current source.
The SFST node is discharged to 0.8V when a fault occurs.
A fault occurs when V
CC
is too low (undervoltage lockout),
current sense voltage is greater than 200mV or the IC’s
thermal (overtemperature) shutdown is tripped. When
SFST discharges, the V
CMP
node voltage is also pulled low
to below the minimum current voltage. Once discharged
and the fault removed, the SFST charges up again. In this
manner, switch currents are reduced and the stresses in
the converter are reduced during fault conditions.
The time it takes to fully charge soft-start is:
t
SS
=
C
SFST
•1.4V
20µA
= 70kΩ •C
SFST
µF
()
Switchers UVLO Pin Function
The UVLO pin provides a user programming undervoltage
lockout. This is typically used to provide undervoltage
lockout based on V
IN
. The gate drivers are disabled when
UVLO is below the 1.24V UVLO threshold. An external
resistive divider between the input supply and ground is
used to set the turn-on voltage.
The bias current on this pin depends on the pin volt-
age and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
dropping the voltage on UVLO. In this manner, hysteresis
is produced.
Referring to Figure 13, the voltage hysteresis at V
IN
is
equal to the change in bias current times R
A
. The design
procedure is to select the desired V
IN
referred voltage
hysteresis, V
UVHYS
. Then:
R
A
=
V
UVHYS
I
UVLO
where:
I
UVLO
= I
UVLOL
– I
UVLOH
is approximately 3.4µA
R
B
is then selected with the desired turn-on voltage:
R
B
=
R
A
V
IN(ON)
V
UVLO
–1
APPLICATIONS INFORMATION
V
IN
R
A
LTC4269-1
(13a) UV Turning On
UVLO
I
UVLO
R
B
V
IN
R
A
LTC4269-1
(13b) UV Turning Off (13c) UV Filtering
UVLO
UVLO
R
B
V
IN
R
A2
R
A1
C
UVLO
R
B
42691 F13
I
UVLO
Figure 13. UVLO Pin Function and Recommended Filtering

LTC4269CDKD-1#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN IEEE 802.3at High Power PD Controller with Flyback Switcher
Lifecycle:
New from this manufacturer.
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